AR# 71846


2018.2 LogiCORE IP MIPI D-PHY v4.1 (rev.1) - MIPI D-PHY TX with 600Mbps line-rate setting has output signal stuck after the first HS transmission.


When the MIPI D-PHY TX line rate is 600Mbps, the output signal gets stuck after the first HS transmission, with dl*_txreadyhs tied to "0" even if dl*_txrequesths is asserted.

How can I fix this issue?


This is a known issue in the MIPI D-PHY v4.1 (rev.1) core, caused by a GUI fault as a result of which you cannot generate the correct clock configuration for 600 Mbps.

All users are recommended to upgrade to the latest version to fix the problem.

  • 2018.2 and earlier - Users can work around the problem by generating the IP with 601Mbps line rate or 599Mbps. You will need to ensure that there is enough bandwidth at the MIPI receive side.
  • 2018.3 and later - This issue has been fixed in Vivado 2018.3 and later versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54550 LogiCORE IP MIPI D-PHY - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions N/A N/A
AR# 71846
Date 05/21/2019
Status Active
Type General Article
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