Version Found: HBM v1.0
Version Resolved: See (Xilinx Answer 69267)
When Write DQ Parity is enabled in the HBM IP GUI certain files need to be modified in order for the feature to be fully functional.
Within the HBM hierarchy there are two *.mem files that need to be modified.
For Implementation, make edits to the following file:
For Simulation, make edits to the following file:
In either case the 'X' in the file name indicates the target HBM stack, either 0 or 1, when both stacks are enabled.
To enable the feature two lines need to be added for each memory controller. These should be placed near the top of the *.mem file.
The first line represents the Memory Controller address and the second line enables the Write DQ parity path:
To Enable Write DQ parity for Stack 1 on MC10, MC11, and MC15:
1) Open the project.srcs/sources_1/ip/hbm_0/hdl/rtl/xpm_internal_config_file_1.mem and project.srcs/sources_1/ip/hbm_0/hdl/rtl/xpm_internal_config_file_sim_1.mem files for editing outside of Vivado.
2) Add the following lines to the top of each *.mem file and then save the changes.
Note: If the IP is reconfigured and output products are generated again, then these files will be overwritten and will need to be modified again.
01/07/2019 - Initial Release