UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 71975

U280-ES1 Known Issues

Description

This Answer Record lists all current Known Issues with the Xilinx Alveo U280-ES1 Data Center Card.

Solution

ES Limitations


Operating Conditions

Issue: Inlet Temperature versus Airflow Requirement for the U280 ES1 Card.

Details: U280 ES1 cards support a maximum inlet temperature of 25C with airflow requirements as stated in the following tables for sea level and 1200m above sea level.

Inlet Temperature versus Airflow Requirement PCIe Card Slot (34.8mm x 106.65mm) at Sea Level for 85C Rated QSFP
Inlet Temperature to the Card (C)Linear Feet per Minute (LFM)Cubic Feet per Minute (CFM)
2560024
Inlet Temperature versus Airflow Requirement PCIe Card Slot (34.8mm x 106.65mm) at 1200m above Sea Level for 85C Rated QSFP
Inlet Temperature to the Card (C)Linear Feet per Minute (LFM)Cubic Feet per Minute (CFM)
2565026

 

Resolution: U280 production cards support a range of inlet temperatures with lower airflow requirements, see the U280 Product Datasheet for details. 


High Bandwidth Memory Controller (CUSTOM MODE ONLY)

Issue: A cross stack transaction can hang the inter-stack channels

Details: In a dual HBM stack configuration with AXI switch global addressing enabled, cross stack memory accesses can lead to a hang of the inter-stack channels. 

Same stack access is unaffected.

The potential hang can occur under the following configuration:

  • AXI switch global addressing enabled
  • Cross stack memory accesses

When a read or a write command is sent from an AXI port that crosses from one switch to the other, the command fails to propagate through, and no error flag or normal response is returned to the AXI port.

The AXI port will ultimately hang as it waits for a response that will never come.

This is a power-on-reset issue.

If the problem does not occur on the first cross-switch transaction, the problem will not occur afterwards.

A device that works for some time does not mean that the device is immune to the problem, as it might occur after the next power-cycle.

Resolution: To avoid potential hang of the inter-stack channels, connect to and access HBM channels from appropriate HBM controller ports, and avoid cross stack memory accesses within the HBM controller. 

Contact Xilinx for other potential work-arounds on U280 ES1 cards. This issue is fixed on U280 production cards with XCU280 production devices.



Issue: AXI-RRESP can be incorrect in some conditions.

Details: The AXI read data slave response (RRESP) can be erroneous in either of the following conditions:

 

  • I enable ECC correction and enable ECC scrubbing
  • I enable ECC correction and a partial word write (read-modify-write) operation.

 

See figure below.


 

 

 

Resolution: To work around this issue, do not use either ECC scrubbing or Partial Word Writes in combination with ECC Correction. 

This issue is fixed on U280 production cards with XCU280 production devices.


Issue: HBM data rate is limited to 1.6 Gbps per pin.

Details: This limitation is from the HBM vendor and silicon used on U280 ES1 cards, and limits maximum bandwidth to 410 GB/s.

Resolution: Under nominal conditions, operating the U280 ES1 cards at maximum HBM data rate of 1.8Gbps per pin (460 GB/s bandwidth) might be achievable. 

This issue is fixed in U280 production cards and with XCU280 production devices.


Power

Issue: Static power on XCU280 ES1 FPGA devices can be higher than on production devices.

Details: Static power is increased for the engineering sample XCU280 ES1 FPGA devices used on U280 ES1 cards. 

XCU280 ES1 devices can exhibit up to 2x higher static power than XCU280 production devices used on U280 production cards.

Resolution: This issue is fixed on U280 production cards with XCU280 production devices.

 

CCIX

 

Issue: Cache Coherent Interface Interconnect for Accelerators (CCIX) support.

Details: CCIX is not fully supported in current SDAccel shell release for U280 ES1 cards

Resolution: Full CCIX support will be available in a future release for U280 ES1 cards, for early access information please contact your local sales representative.


Known Issues - Active

 

Hardware Emulation

Issue: Hardware emulation uses extra host memory.

Details: In some applications, hardware emulation runs can use ~10GB of memory.

Resolution: This will be fixed in a future shell release.

 

SDAccel Shell

Issue: Platform info resource summary is incorrect.

Details: Platform info reports per SLR information correctly but the total summary of resources is incorrect. 

Please use per SLR information.

Resolution: This will be fixed in a future SDAccel release.



Issue: PLRAM resources resize above 128kb (Default) might fail.

Details:  If the PLRAM resources are resized above 128kB (the default size), the PLRAM resize can fail, resulting in data accesses being corrupted.

Resolution: This will be fixed in a future SDAccel release.   User logic should not attempt to upsize the PLRAM resource sizes above the defaults in the shell.

 


 

Host-Card Interoperability

(Xilinx Answer 72640)Alveo Data Center Accelerator Card - Card might not return after PCI Express In-Band Hot reset on AMD EPYC Host

Known Issues - Resolved


Card Management

Issue: HBM Temperature monitoring is not currently available.

Details: As HBM temperature is not available, the FPGA temperature can still be used for monitoring threshold values as the FPGA and HBM temperatures are well correlated.

Resolution: HBM Temperature monitoring is resolved in the 201910_1 Shell Reset


Issue: Memory ECC monitoring and error checking is not currently available.

Details: ECC error checking is not enabled on the DDR/HBM memory resources.

Resolution: DDR/HBM memory ECC support is available in the 201910_1 Shell Release.


Issue: QSFP temperature monitoring is not currently available.

Details: The SDAccel shell and Xilinx Runtime do not currently support the card QSFPs.

Resolution: This is available in the 201910_1 Shell Release.

 

Hardware Emulation

Issue: Hardware emulation limits the maximum allowed buffer size.

Details: Within an HBM memory resource, the maximum buffer cannot be 256MB as on a hardware target, it is 256 MB minus 4KB (this is space needed for emulation content)

Resolution: This is resolved in the 2019.1 SDAccel release.

  

xbutil

Issue: xbutil query output is garbled.

Details: xbutil query output shows some incorrect memory allocations and memory types.

Resolution: This is resolved in the 201910_1 XRT release (201910_1 Shell)

 

SDAccel Shell

Issue: The current shell has 32-bit BARs, and conflicts can happen in systems with multiple PCIe cards.

Details: The BIOS/OS can fail to allocate memory for all cards and there might be boot up issues with the machine.

Resolution: This is resolved in 201910_1 Shell size

 

Debug

Issue: Combining a MicroBlaze Debug Module and System ILA within a kernel is not supported.

Details: The debug bridge will be detected but the System ILA will not function.

Resolution: This is resolved in the 201910_1 Shell size

AR# 71975
Date 08/12/2019
Status Active
Type Known Issues
Boards & Kits
  • Alveo U280
Page Bookmarked