Version Found: v3.0 Version Resolved and other Known Issues: (Xilinx Answer 70927)
The tactical patch provided with this answer record contains the following fixes and enhancements.
* Bug Fixes: This patch contains all previously released fixes for the 2018.2 version, detailed in Mailbox interrupt issue fix: Mailbox interrupts were generating only from PF vectors and were not able to generate from other vectors Interrupts not received properly with mix of direct interrupts and indirect interrupts AXI-MM only with completion option not working Write back coalesce buffer depth of 32 and 64 not working, 32 depth issue is fixed and 64 depth is not allowed Prefetch cache depth GUI parameter propagation issue C2H write back timer deletion issue: Injection of a timer immediately after deletion causes deletion to stall and resulting in multiple timers Marker response not working when queue is disabled Issue with more than 8 interrupt vectors per function using Tcl option CONFIG.adv_int_usr Expansion ROM space (EPROM selected in last BAR) read/write access issue Example design issue: Completions are not received for ST C2H transfers which follows mix payload transfers (immediate data and payload data) Removed empty cycle after SOP in C2H DMA write engine to improve performance * Feature Enhancement: Enabled slot clock configuration option from the GUI (Xilinx Answer 70927) This article is part of the PCI Express Solution Centre (Xilinx Answer 34536) Xilinx Solution Center for PCI Express
This issue will be fixed in the next release of the core.
Please install the patch in Vivado 2018.3 as described in the readme file included in the patch ZIP file.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.
Revision History: 02/26/2019 - Initial Release 03/11/2019 - Updated the tactical patch with Rev2
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