AR# 72057
|7 Series Integrated Block for PCIe (Vivado 2018.3) - Gen2x4 Example Design Fails Timing with AC701 Evaluation Kit
Description
Version Found: v3.3 (Rev10)
Version Resolved and other Known Issues: See (Xilinx Answer 54643)
The 7 Series Integrated Block Example Design configured for Gen2x4, with Tandem PCIe enabled, does not meet timing in Vivado 2018.3 with default synthesis and implementation strategies.
The path that is failing timing is seen below:
This article is part of the PCI Express Solution Centre
| (Xilinx Answer 34536) | Xilinx Solution Center for PCI Express |
Solution
To work around this issue, you can use the Implementation Strategy "Performance_ExplorePostRoutePhysOpt" in order to get timing to pass.
set_property strategy Performance_ExplorePostRoutePhysOpt [get_runs impl_1]
Revision History:
03/01/2019 - Initial Release
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Linked Answer Records
Master Answer Records
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 54643 | 7 Series Integrated Block for PCI Express - Release Notes and Known Issues for Vivado 2013.1 and newer tool versions | N/A | N/A |
| AR# 72057 | |
|---|---|
| Date | 03/01/2019 |
| Status | Active |
| Type | Known Issues |
| Tools | |
| IP | |
| Boards & Kits | |
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