Version Found: v3.3 (Rev10)
Version Resolved and other Known Issues: See (Xilinx Answer 54643)
The 7 Series Integrated Block Example Design configured for Gen2x4, with Tandem PCIe enabled, does not meet timing in Vivado 2018.3 with default synthesis and implementation strategies.
The path that is failing timing is seen below:
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
To work around this issue, you can use the Implementation Strategy "Performance_ExplorePostRoutePhysOpt" in order to get timing to pass.
set_property strategy Performance_ExplorePostRoutePhysOpt [get_runs impl_1]
03/01/2019 - Initial Release
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