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AR# 72076

Example design with PL-PCIe Root Port in ZCU106 and PS-PCIe Endpoint in UltraZed

Description

This answer record provides a document with an "Example design with PL-PCIe Root Port in ZCU106 and PS-PCIe Endpoint in UltraZed" in a downloadable PDF to enhance its usability. 

Answer Records are Web-based content that are frequently updated as new information becomes available. 

Visit this answer record to obtain the latest version of the PDF.


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

The document attached to this answer record describes steps for creating an example design with PL-PCIe Root Port in a ZCU106 board and a PS-PCIe Endpoint in an UltraZed card.

The document goes through the detailed steps for design creation for ZCU106 board and UltraZed card in Vivado, and PetaLinux Image generation for the ZCU106 board and the initialization mechanism for UltraZed as an endpoint.

The relevant files have been provided in the zip file. The instructions provided in the document have been provided only as a reference.

The steps could vary depending on the tool versions used.

Revision History:

03/25/2019 - Initial Release

Attachments

Associated Attachments

Name File Size File Type
Xilinx_Answer_72076.zip 11 KB ZIP
Xilinx_Answer_72076_ZCU106_RC_UltraZed_EP.pdf 7 MB PDF
AR# 72076
Date 08/22/2019
Status Active
Type General Article
IP
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