AR# 72113


Zynq UltraScale+ MPSoC, PS DDR - DDR4 training occasionally fails on ZCU102 and ZCU106 boards using newer DIMMs


Newer DIMMs in ZCU102 (>0432055-05) and ZCU106 (>0432032-02) boards are in a small number of cases failing in boot with no FSBL messages output.

This is occurring when using a 2018.3 FSBL or pre-built boot images from the 2018.3 PetaLinux BSP.

The failure behavior of boot is that psu_init code gets stuck in polling the DDR_PHY(0xFD080030) register.

The value (0x80C000FF) from the address DDR_PHY (0xFD080030) is showing a Write Leveling Adjustment Error and DQS Gate Training Error.

The issue can be seen very intermittently by power cycling the board continuously. 

How do I resolve this?


The issue was due to DDR-PHY training happening twice for the new DIMM (once in the psu_init code and once in the DDR SPD code).

The serial numbers with the newer DIMMs can be found in (Xilinx Answer 71961).


To work around this issue, you can replace the FSBL source code files with the attached .c/.h files in

This will ensure that the training is executed only once.

For PetaLinux flows, apply the attached .patch file to FSBL recipes. 

For more information, refer to (UG1144) or

This issue is planned to be fixed starting in Vivado 2019.1.


Associated Attachments

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
71961 Design Advisory for Zynq UltraScale+ MPSoC ZCU102 and ZCU106 Evaluation Kits - DDR4 SODIMM change N/A N/A
AR# 72113
Date 03/27/2019
Status Active
Type General Article
Boards & Kits
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