AR# 72230

UltraScale/UltraScale+ - RLDRAM3 IP - Known Issues with RLDRAM3 and SEM IP Interaction

Description

Version Found: RLDRAM3 v1.3

Version Resolved: See (Xilinx Answer 69037)

The purpose of this Answer Record is to highlight the possibility of negative interactions between the Soft Error Mitigation IP and RLDRAM3 cores.

If you are creating a new RLDRAM3 design and intend to use the SEM IP, please contact Xilinx Support.

Solution


  • Always disable the SEM IP when the RLDRAM3 interface is running calibration at startup.  This also applies to all high speed external memory interfaces.
  • It is not recommended to use the SEM IP when the RLDRAM3 interface is running at 800MHz or faster.
  • There is a risk of post calibration data errors with RLDRAM3 interfaces that span multiple FPGA banks when the SEM IP is enabled. 
  • For RLDRAM3 designs with an 18-bit data bus and address multiplexing enabled, it is possible to fit the entire interface in one FPGA bank.
    Other configurations will not be able to fit in a single FPGA bank and are at risk when the SEM IP is enabled.

Xilinx does not recommend using the SEM IP when RLDRAM3 cores are present in the design.

Revision History:

05/08/2019 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
69037 UltraScale/UltraScale+ RLDRAM3 - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
70214 UltraScale/UltraScale+ - RLDRAM3 IP - Tactical Patch for SEM and RLD integration N/A N/A
AR# 72230
Date 05/08/2019
Status Active
Type Known Issues
Devices More Less
Tools
IP