AR# 72238

Zynq UltraScale+ MPSoC - Vivado Readback Verify fails when PL SYSMON is configured via APB Slave Interface

Description

The control and configuration registers of the PL SYSMON can be accessed via DRP interfaces within the PL domain, or APB Slave Interface from the PS.

The Readback Verify feature checks the bitstream programmed into the device against an MSK file.

Any change of the PL SYSMON configuration after programming of the bitstream, if not masked, will be detected as an error during Vivado Readback Verify.

  • If the PL SYSMON is instantiated in the design with the DRP Interface enabled, these "differences" are masked by the MSK file and no error will be reported.
  • If the PL SYSMON is not instantiated in the design but is configured from the PS using the APB Slave Interface, these "differences" will be reported as "errors" and there is no method to mask them.

Solution

In a case where the PL SYSMON is not instantiated in the design, but is configured from the PS using the APB Slave Interface, you can do the following:

  1. Ignore those errors. If you change 3 bits in the PL SYSMON configuration, you should expect 3 errors reported by Readback Verify.
  2. Perform the Readback Verify prior to changing the PL SYSMON configuration.
  3. Re-Configure the PL SYSMON back to its original setup before performing the Readback Verify.
AR# 72238
Date 05/02/2019
Status Active
Type General Article
Devices
Tools