General Description: After starting up a CORE Generator session, if either a Virtex Dual-Port or Single-Port Block Memory is the first core that is generated, the EDIF implementation netlist may be invalid. In some cases, there may be nets that are shorted together. For example, an address bit may be shorted with the CLK signal:
In the snippet above, addr<0> and CLK are shorted together because they were both renamed to "N2". This can cause "duplicate net" errors when simulating a design containing such a core in Foundation.
** This problem was fixed in Service Pack 2 for the 2.1i release. **
Previously suggested work-around (provided for reference only):
The problem is only seen when the core is generated in GUI mode; when the core is generated in batch mode, this problem does not occur.
To regenerate the core in batch mode, read in the .XCO file by going to File->Execute Command File, and specifying the .XCO file as input.
** OBSOLETE **
The problem has been only seen when you generate a Dual Port or Single Port Virtex Block RAM immediately after starting up the CORE Generator. You must regenerate the respective core a second time within the same session to get a valid EDIF netlist.