AR# 72389

Zynq UltraScale+ MPSoC (Vivado 2019.1) - PL-PCIe Root Port - Driver Compilation Fails

Description

When a Zynq UltraScale+ MPSoC PL Bridge is Root Port (DMA/Bridge Subsystem for PCI Express - Bridge mode) and driver enabled in PetaLinux, the driver compilation fails.

The compilation failure is due to a change in PCIe subsystem APIs in Kernel 4.19.


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

To address the issue, please install the tactical patch attached to this answer record. 

The patch removes the deprecated API of_pci_get_host_bridge_resources () and uses the new kernel API devm_of_pci_get_host_bridge_resources() to fix the compilation error.

Please refer to the link below for guidance on installing the patch.

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842475/PetaLinux+Yocto+Tips#PetaLinuxYoctoTips-PatchingtheLinuxKernelofaPetaLinuxProject

Revision History:

05/30/2019 - Initial Release

Attachments

Associated Attachments

AR# 72389
Date 01/06/2020
Status Active
Type Known Issues
IP