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AR# 7240

FPGA Express - Is it possible to infer signed arithmetic modules in VHDL or Verilog?

Description

Keywords: signed, Verilog, Express, modules

Urgency: Standard

General Description:
Is it possible to infer signed arithmetic modules in VHDL or Verilog?

Solution

1

VHDL

Signed modules can be inferred, but it is currently not possible to infer both signed and unsigned operators in the same entity-architecture pair.

Please see the FPGA Express online help topic "Arithmetic and Relational Module Inference Examples" for examples and more information.

2

Verilog

Currently, it is not possible to infer signed modules in Verilog.

For more information, please refer to the FPGA Express online help topic "Arithmetic and Relational Module Inference Examples".
AR# 7240
Date Created 08/11/1999
Last Updated 08/11/2003
Status Archive
Type General Article