AR# 72404

Simulation Libraries failures for Vivado 2019.1

Description

In the 2019.1 release, compile_simlib fails to compile some IPs for VCS and Cadence Simulators (IES and Xcelium).

VCS:

The "hdmi_gt_controller_v1_0_0" IP fails to compile with the following error message:

Error-[ITSFM] Illegal `timescale for module <vivado install directory>/data/ip/xilinx/hdmi_gt_controller_v1_0/hdl/src/verilog/hdmi_gt_controller_v1_0_lib.sv

IES and Xcelium:

The "sync_ip" IP fails to compile with the following error message:

ncvlog: *E,ERRIPR: error within protected source code

Solution

To work around this issue for the "hdmi_gt_controller_v1_0_0" IP, add "`timescale 1ns/1ps" to the following file and re-generate the compiled libraries.

$XILINX_VIVADO/data/ip/xilinx/hdmi_gt_controller_v1_0/hdl/src/verilog/hdmi_gt_controller_v1_0_dru.sv.

You can ignore these failures if your design does not include the IPs in question.

If you are using these IPs in the design, other simulators can be used for simulation as a work-around.

The issue will be fixed in the 2019.2 release.

AR# 72404
Date 08/09/2019
Status Active
Type Known Issues
Tools