AR# 72412

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Queue DMA subsystem for PCI Express (PCIe) (Vivado 2019.1) - Timing failure on certain devices with specific configurations

Description

Version Found: v3.0 (Rev1)

Version Resolved and other Known Issues: (Xilinx Answer 70927)

Timing failures can occur in a QDMA design for the following configurations and devices:

  • Gen3x16 - Device: VU11p
  • Gen3x16 - Device: XQZU7ev
  • Gen3x8   - Device: ZU25dr



This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express

Solution

This is a known issue which is planned to be fixed in a future release of the tool. 

As a work-around, use the 'Performance Explorer' implementation strategy.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.


Revision History:

  • 05/29/2019 - Initial Release
AR# 72412
Date 05/29/2019
Status Active
Type Known Issues
IP
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