AR# 72427


LogiCORE IP Video Processing Subsystem (VPSS) v2.0 - Why do I see visual artifacts from the scaler when using UltraRAM?


When using the scaler feature of the LogiCORE IP Video Processing Subsystem (VPSS) IP on UltraScale/UltraScale+ architecture with "Use UltraRAM for Line Buffers" enabled, I see visual artifacts.

What is the reason for this issue?


This is a known issue with the HLS synthesis tool which generates the RTL for the LogiCORE IP Video Processing Subsystem (VPSS) IP.

It is generating incorrect RTL when using UltraRAM.

This issue is fixed in Vivado 2018.2.

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AR# 72427
Date 06/05/2019
Status Active
Type Known Issues
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