Why do I see link errors on the TX when using QPLL0 and QPLL1 to switch line rates on the RX between 11.88 Gbps and 11.88/1.001 Gbps?
I am using the SMPTE UHD-SDI IP and SMPTE UHD-SDI Receiver and Transmitter Subsystems with QPLL0/1 as shown in the diagram below.
Switching the SMPTE UHD-SDI Receiver from 11.88Gbps to 11.88/1.001Gbps can inject errors into the SMPTE UHD=SDI Transmitter channel resulting in CRC errors at the 12G-SDI Sink.
This is due to a limitation of the UltraScale+ GTH/GTY that is addressed in (Xilinx Answer 72254).
This issue only applies to the SMPTE UHD-SDI Receiver and Transmitter in the below use case:
For users who need both 12G-SDI Receive and Transmit and need them to operate independently, here are the recommended solutions:
For additional information see the following documentation:
The SMPTE UHD-SDI Receiver Subsystem - Audio-Video Loopback for the KCU116 board example design has been updated in the 2019.2 release and later versions to implement the above clocking recommendations.
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