Version Found: DDR4 v2.2 (Rev. 7) and DDR3 v1.4 (Rev. 7)
Version Resolved: See (Xilinx Answer 58435)
Currently in Vivado 2019.1 and 2019.2 there are restrictions on placing memory interfaces in Bank 46 or Bank 25 of the Space Grade Kintex UltraScale XQRKU060 device.
Depending on your flow you will either encounter an "Unable to place ports" error with the Byte Planner tool or with a fixed pinout you will see the following error at implementation:
The tools are preventing any memory interface signals from being be assigned to any of the available bytes of Bank 46 or Bank 25.
In Bank 46 Byte 2, the N7 (A38) and N9 (B39) sites are not bonded out. In Bank 25 Byte 1, site N3 (AV39) is not bonded out.
The restriction is due to the MIG tool and assumptions it makes about the site availability within Select I/O Bytes and how it handles assignment when generating the PHY.
Currently the work-around is to apply the tactical patch attached to this Answer Record.
This behavior is fixed natively in Vivado 2020.1 and memory interfaces will be allowed to use Bank 46 or Bank 25 if data bytes aren't placed in the partial bytes of Bank 46 Byte 2 or Bank 25 Byte 1.
In order to generate a memory interface which uses Bytes within Bank 46 or Bank 25 targeting the Space Grade Kintex UltraScale XQRKU060 Device, please apply the tactical patch attached to this Answer Record to your Vivado installation.
Additionally, when starting your Vivado session enter the following command in the Tcl console to ignore the DRC warnings generated by using Bank 46 or Bank 25:
set_param memory.ignoreSpecialBankRules true
After applying the patch and setting the parameter to ignore the Bank 46 and Bank 25 DRC checks you will be able to generate a valid memory interface.
Limitations when using the patch:
Do not assign any memory interface signals to Bank 46 Byte 2 or Bank 25 Byte 1.
Limitations with Vivado 2020.1 and later:
Do not assign any data bytes to the partial bytes in Bank 46 Byte 2 or Bank 25 Byte 1.