AR# 72586

2018.x Vivado Synthesis - Incorrect Logic Generation for FSM

Description

In the 2018.x release of Vivado Synthesis, there is a known issue where the synthesizer generates incorrect logic when the state machine has the below transition and coding style.

Here is an example of state a transition graph and its RTL which will trigger this bug in the tool:


 

 case (state)
                ...
                STATE1, STATE2: begin
                    ...
                    if (sig1 || sig2) begin
                        state       <= STATE4;
                    end
                    else
                        state       <= STATE3;
                    end
                end
 

Please note that this issue will only occur if the user state transition graph is similar to above state transition graph AND the code is using the below RTL style:

 
 case (state)
                ...
                STATE1, STATE2: begin
                ...

Solution

In order to avoid this issue in 2018.x versions, please change the above code to match the following:

 
  case (state)
                ...
                STATE1: begin
                ...
                STATE2: begin
                ...
 

This issue has been fixed in the 2019.1 release.

AR# 72586
Date 07/25/2019
Status Active
Type General Article
Tools