AR# 72605

2019.1 Zynq UltraScale+ MPSoC VCU - Why does the Zynq UltraScale+ MPSoC VCU Encoder HEVC EnableSkip setting cause encoding to stall after the 600th frame?

Description

Why does the Zynq UltraScale+ MPSoC VCU Encoder HEVC EnableSkip setting cause encoding to stall after the 600th frame?

Solution

This is a known issue with the Zynq UltraScale+ MPSoC VCU - LogiCORE H.264/H.265 Video Codec Unit (VCU) that can occur when using the EnableSkip setting with HEVC encoding.

The issue occurs due to IDR pictures consuming higher bits, and being marked for skip.

As per the HEVC standard, DPB management is done before encoding the picture, and an IDR picture removes all previous references from the list.

If the current IDR is marked for skip due to low cpbsize / target bit rate, the encoder does not have any reference frame to encode the next P frame, leading to a deadlock.

The fixes below will cause the application to issue an exception and close instead of hanging.

  • 2019.1 - Users can work around this issue using one of the following options.
    • Do not use the EnableSkip option.
    • Download the PetaLinux Recipes and Patch files from (Xilinx Answer 72324) to work around this issue.
      Note: This fix avoids the frame skip for all IDR pictures, but it can cause an HRD VBV buffer overflow violation for this picture.

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AR# 72605
Date 09/11/2019
Status Active
Type General Article
Devices
Tools
IP