AR# 72690

UltraScale+ FPGA Integrated Endpoint Block for PCI Express (Vivado 2019.1) - PCIe core returning Error code 05 for completions received for ATS requests

Description

Version Found: v1.3 Rev5 (Vivado 2019.1)

Version Resolved and other Known Issues: (Xilinx Answer 65751)

 

When an End Point receives a completion for an ATS request, it is possible that the PCIe Hard block will present the TLP to the user with Error code "05".

Error code "05" is described in (PG213) as follows:

"Error in starting address. The low address bits in the Completion TLP header did not match with the starting address of the next expected byte for the request.
The user application should discard any data that follows the descriptor.
In addition, if the Request Completed bit in the descriptor is not set, the user application should continue to discard the data subsequent Completions for this tag until it receives a completion descriptor with the Request Completed bit set.
On receiving a completion descriptor with the Request Completed bit set, the user application can discard the corresponding request."


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

This is a known silicon issue when crossing a 4KB boundary. To work around the issue, ignore the error code of 0x5 for ATS requests.

Revision History:

10/11/2019 - Initial Release

AR# 72690
Date 10/11/2019
Status Active
Type Known Issues
Devices More Less
IP