This answer record provides an Interrupt Debug Document for the following IPs targeting UltraScale and UltraScale+ devices in a downloadable PDF to enhance its usability.
- UltraScale FPGA Integrated Endpoint Block for PCI Express
- UltraScale+ FPGA Integrated Endpoint Block for PCI Express
- DMA/Bridge Subsystem for PCI express
- AXI Bridge Subsystem or PCI express
Answer Records are Web-based content that are frequently updated as new information becomes available.
Visit this answer record to obtain the latest version of the PDF.
This article is part of the PCI Express Solution Centre(Xilinx Answer 34536)
Xilinx Solution Center for PCI Express
Please download the Ultrascale and Ultrascale+ PCIe Interrupt debug guide attached with this answer record.
This document provides the steps involved to initiate Legacy, MSI and MSI-x interrupts with different IP cores targeting UltraScale and UltraScale+ devices.
Please also refer to (Xilinx Answer 58495)
which provides theoretical background and the steps to initiate Legacy and MSI interrupts with the 7 Series Integrated block IP core.
09/20/2020 - Initial Release
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