This Design Advisory covers an issue with UltraScale+ GTH/GTY transceivers where GTPOWERGOOD might not assert after power-up.
The *_delay_powergood.v module is included in all UltraScale+ GTH/GTY transceivers.
Some builds of the GTH/GTY design might have the GTPOWERGOOD from the *_delay_powergood.v module stuck low, while the FPGA power rail is good and GT primitive output GTPOWERGOOD is asserted.
The symptom of the failure is that the GT Wizard IP does not come out of the reset state (for example, reset does not complete and/or the PLL is not locked even across reset/power cycles).
An update will be made to the *_delay_powergood.v module in the Vivado 2019.2 release of the UltraScale Transceiver Wizard IP.
For UltraScale+ GTH/GTY designs targeting Vivado versions between 2017.2 and 2019.1.3:
Steps to follow:
1) Open the project, or a routed DCP.
2) Use the following Tcl Command:
write_xdc -exclude_physical all_constraints.xdc
3) Edit the generated all_constraints.xdc and comment out the associated delay_powergood set_case_analysis and set_false_path constraints:
Note: the bolded * above could vary depending on the number of lanes (e.g. 1, 2, ...).
4) Use the following Tcl commands:
5) Run timing check using Report Timing Summary.
6) Check if any hold time violations are reported in the *_wait_cnt_reg* paths, for example:
To apply the modified *_delay_powergood module, update the below HDL files in the Vivado install directory with the files attached to this Answer Record and regenerate the wizard IP.
2018.3 Vivado = gtwizard_ultrascale_v1_7_5_gtye4_delay_powergood
2019.1 Vivado = gtwizard_ultrascale_v1_7_6_gtye4_delay_powergood
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