AR# 72746

Design Advisory for UltraScale+ GTH/GTY Transceivers: GTPOWERGOOD might not assert after power-up

Description

This Design Advisory covers an issue with UltraScale+ GTH/GTY transceivers where GTPOWERGOOD might not assert after power-up.

The *_delay_powergood.v module is included in all UltraScale+ GTH/GTY transceivers. 

Some builds of the GTH/GTY design might have the GTPOWERGOOD from the *_delay_powergood.v module stuck low, while the FPGA power rail is good and GT primitive output GTPOWERGOOD is asserted. 

The symptom of the failure is that the GT Wizard IP does not come out of the reset state (for example, reset does not complete and/or the PLL is not locked even across reset/power cycles).

Solution

An update will be made to the *_delay_powergood.v module in the Vivado 2019.2 release of the UltraScale Transceiver Wizard IP.

For UltraScale+ GTH/GTY designs targeting Vivado versions between 2017.2 and 2019.1.3:

  • For all new designs, use the modified *_delay_powergood modules attached to this answer record.
  • For existing designs, check design timing by following the steps below even if the gtpowergood issue is not observed.
     
    • If hold time violations are reported on the *_wait_cnt_reg* paths, apply the modified *_delay_powergood module.
    • If there is no hold time violation, no wizard IP regeneration is required.

Steps to follow:

1) Open the project, or a routed DCP.

2) Use the following Tcl Command:

write_xdc -exclude_physical all_constraints.xdc

3) Edit the generated all_constraints.xdc and comment out the associated delay_powergood set_case_analysis and set_false_path constraints:

 

##set_false_path -through [get_pins -filter {REF_PIN_NAME=~*Q} -of_objects [get_cells -hierarchical -filter {NAME =~ *gen_pwrgood_delay_inst[*].delay_powergood_inst/gen_powergood_delay.pwr_on_fsm*}]] -quiet
##set_case_analysis 1     [get_pins -filter {REF_PIN_NAME=~*Q} -of_objects [get_cells -hierarchical -filter {NAME =~ *gen_pwrgood_delay_inst[*].delay_powergood_inst/gen_powergood_delay.pwr_on_fsm*}]] -quiet

 

Note: the bolded * above could vary depending on the number of lanes (e.g. 1, 2, ...).

 

4) Use the following Tcl commands:

reset_timing
read_xdc all_constraints.xdc

5) Run timing check using Report Timing Summary.

6) Check if any hold time violations are reported in the *_wait_cnt_reg* paths, for example:

 

wait_cnt_reg.PNG

 

To apply the modified *_delay_powergood module, update the below HDL files in the Vivado install directory with the files attached to this Answer Record and regenerate the wizard IP.

./data/ip/xilinx/gtwizard_ultrascale_v1_7/hdl/gtwizard_ultrascale_v1_7_gthe4_delay_powergood.v 

./data/ip/xilinx/gtwizard_ultrascale_v1_7/hdl/gtwizard_ultrascale_v1_7_gtye4_delay_powergood.v 

Notes:

  • UltraScale GTH/GTY designs are not impacted.
  • PCIe IP designs are not impacted.
  • To regenerate IP, first select Reset Output Products... followed by Generate Output Products...
  • The RTL module name needs to be modified to match the RTL module name for each Vivado release.

 

For Example:

2018.3 Vivado = gtwizard_ultrascale_v1_7_5_gtye4_delay_powergood

2019.1 Vivado = gtwizard_ultrascale_v1_7_6_gtye4_delay_powergood

Attachments

Associated Attachments

Name File Size File Type
AR72746__GTPOWERGOOD_Design_Advisory.zip 4 KB ZIP
AR# 72746
Date 10/22/2019
Status Active
Type Design Advisory
Devices
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IP