AR# 72805


Zynq UltraScale+ MPSoC PS SYSMON Clocking


The Zynq UltraScale+ MPSoC TRM includes a section that details PS and PL SYSMON Clocking.

It states that the digital reference clock for the SYSMON is LPD_LSBUS_CLK:

"The SYSMON clock is driven by an interface clock. The interface clock is divided down to generate the ADC clock using the CONFIG_REG2 [clock_divider] bit field.

  • PL SYSMON clock is based on LPD_LSBUS_CLK (APB bus) or PL_DCLK (when the SYSMONE4 primitive is instantiated).
  • PS SYSMON clock is based on LPD_LSBUS_CLK (APB bus)"

This is incorrect and will be fixed in a future release of the TRM.

This Answer Record details the clocking infrastructure for the PS and PL SYSMON.


The diagram shows the clocking structure for the PS and uninstantiated PL SYSMON.




The PSSYSMON_REF_CLK feeds the digital clock to the PS SYSMON and the PL SYSMON when it is not instantiated.

This clock is generated based on the settings in the PSSYSMON_REF_CTRL Register.





 This register contains bits to select the incoming PLL clock.


The input clock can come from the RPLL or IOPLL (both of these are equipped with a divide by 2 output) or the DPLL_CLK_TO_LPD, which is a divided version of the DPLL. 

This divisor can be seen in the DPLL_TO_LPD_CTRL register.

IOPLL settings can be seen in the IOPLL_CTRL register.

RPLL settings can be seen in the RPLL_CTRL register. These are both part of the CRL_APB register group. 


PSSYSMON_REF_CTRL also sets two dividers, DIVISOR0 and DIVISOR1 that produce the PSSYSMON_REF_CLK.


The PSSYSMON_REF_CLK is then passed to the SYSMON units and from there it is further divided in the SYSMON configuration registers to produce the ADC clock.


It is also possible to examine the clocking set up from the Processor Configuration Wizard in Vivado. 

You can see in this example that the IOPLL is selected.

Its VCO is 3000Mhz and its DIV2 setting is enabled. This means that 1500Mhz is passed to the PSSYSMON_REF_CTRL block.

The PSSYSMON_REF_CLK is requested to be 50MHz.

DIVISOR0 is set to 30 and DIVISOR1 is set to 1 in this case.







AR# 72805
Date 10/02/2019
Status Active
Type General Article
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