Version Found: v1.3 Rev5 (Vivado 2019.1)
Version Resolved and other Known Issues: (Xilinx Answer 65751)
When using Legacy interrupts, the following sequence of steps can cause the Legacy interrupt to be held asserted, resulting in continuous INTx messages being sent upstream.
As per the PCIe specification, the PCIe integrated Block in End Point will need to send a "Deassert_INTA" message after step 2 above.
This does not happen with the PCI Express Integrated Block in UltraScale (or) UltraScale+ devices.
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
This is a known silicon issue. A work-around is provided below.
10/14/2019 -- Initial Release