AR# 72916


UltraScale/UltraScale+ (Vivado 2019.1) - PCI Express Integrated Block does not respond correctly to the "interrupt_disable" bit setting for Legacy interrupts


Version Found: v1.3 Rev5 (Vivado 2019.1)

Version Resolved and other Known Issues: (Xilinx Answer 65751)

When using Legacy interrupts, the following sequence of steps can cause the Legacy interrupt to be held asserted, resulting in continuous INTx messages being sent upstream. 

  1. Endpoint asserts Legacy interrupt (for example, INTA)
  2. The host writes to the endpoint configuration space to set the "interrupt disable" bit of the command register to 1'b1

As per the PCIe specification, the PCIe integrated Block in End Point will need to send a "Deassert_INTA" message after step 2 above. 

This does not happen with the PCI Express Integrated Block in UltraScale (or) UltraScale+ devices.

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express


This is a known silicon issue. A work-around is provided below.

  1. Assert the cfg_interrupt_int signal in the endpoint.
    It sends an assert_INTA message to the host.
  2. The driver in the host sets the Interrupt Disable bit in the FPGA configuration space.
  3. Implement a register in the FPGA accessible to the driver to monitor bit3 (INTx Disable) of the cfg_function_status output from the endpoint.
    • You will need to unset the Interrupt disable bit in the FPGA configuration space, otherwise de-asserting cfg_interrupt_int will not generate a deassert_INTA message when the interrupt disable bit is set in the configuration space.
  1. de-assert cfg_interrupt_int after bit3 in the cfg_function_status output is asserted. The endpoint will send deassert_INTA message to the host.

Revision History:

10/14/2019 -- Initial Release

AR# 72916
Date 10/14/2019
Status Active
Type Known Issues
Devices More Less
IP More Less
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