AR# 72980


Vivado - Resolving [Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I1


This answer record describes how to resolve opt_design Opt 31-67 errors.

[Opt 31-67] Problem: A LUT2 cell in the design is missing a connection on input pin I1, which is used by the LUT equation. This pin has either been left unconnected in the design or the connection was removed due to the trimming of unused logic. The LUT cell name is: sub_inst/temp_ab_inferred_i_1.

The error could also specify a different LUT primitive such as a LUT3 or LUT6, or a different LUT input such as I0, I2, or I5.


This error is typically seen when implementing a design where there are netlists that are synthesized separately, but them merged together for the implementation process. 

The LUT input from one netlist is expected to be driven from outside of that netlist. The error message occurs when that connection is missing.

For example, the error can occur when using IPs that are synthesized out of context (OOC) if the inputs are not properly connected.

The steps to trace the issue back to the source are as follows.

1) Open the Synthesized Design. From a project, this can be done from the Flow Navigator as seen below.


2) Select the object from the error message and build a schematic:

select_objects [get_cells {sub_inst/temp_ab_inferred_i_1}]

Press F4 once it is selected.

3) Next, trace the connectivity of the pin in question (I1) to its driver. 

This can be done by selecting the pin, right-clicking, and selecting Expand Cone > To Leaf Cells

Alternatively, double clicking on the pin will expand the connected net.


4) Trace through as many hierarchies as needed to find where it is disconnected (n/c).


5) Right-click on the hierarchy where the net becomes disconnected (sub_inst), right-click again, and select Go to Source.


6) This will lead to an RTL source, where the instantiation can be analyzed for possible connectivity problems. 

Below, the B pin of sub_inst needs to be connected.


If following the connectivity leads to a driver cell that is fully connected, (Xilinx Answer 58616) can be used to trace any optimizations that would lead to the LUT pin being unconnected.

AR# 72980
Date 11/20/2019
Status Active
Type General Article
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