AR# 72987


ZYNQ UltraScale+ VCU DDR4 Controller v1.0 - VCU DDR4 Controller IP synthesis errors when running the generate output products operation in Vivado 2019.1


When using the VCU DDR4 Controller IP, I am receiving the below synthesis errors while running the generate output products operation with the out-of-context per IP synthesis option:

[Synth 8-5809] Error generated from encrypted envelope.

[Synth 8-285] failed synthesizing module 'DDR4Ctrl_1'

[Synth 8-6156] failed synthesizing module 'vcu_ddr4_controller_v1_0_1_ba317'


This is a known issue in the Zynq UltraScale+ MPSoC VCU DDR4 Controller IP v1.0 in Vivado 2019.1.

It is resolved in the Zynq UltraScale+ MPSoC VCU DDR4 Controller IP v1.1 in the 2019.2 release.

You can work around this issue using the following steps:

  1. Create a project with a Zynq UltraScale+ MPSoC device
  2. Call the Zynq UltraScale+ VCU DDR4 Controller into the block design
  3. Open the IP for configuration and change the memory part from the default part to any of the memory parts listed in the GUI
  4. Select the default memory part and click the OK button on the IP GUI
  5. Save the block design and perform the block design validate check operation
  6. Run the generate output products operation, by selecting the out-of-context synthesis option on the pop up window.
  7. Confirm that the generation completes without any failures

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
54490 Zynq UltraScale+ VCU DDR Controller - Release Notes and Known Issues for Vivado 2018.1 and later versions N/A N/A
AR# 72987
Date 11/20/2019
Status Active
Type Error Message
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