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AR# 7300

LogiCORE PCI - Inserting initial latency in a target design

Description

General Description:  

What is the methodology for inserting wait states into a target transaction?

Solution

In Chapter 6 of LogiCORE PCI Design Guide ("Target Data Phase Control"), Example 3 describes initial latency and how initial wait states should be inserted. (LogiCORE PCI Design Guides are available at: http://www.support.xilinx.com/products/logicore/coredocs.htm#datasheets) This Answer Record discusses the exact way to read the pseudo code.  

 

On Clock Cycle 1, the Address is valid on AD_IO (the external PCI bus) and FRAME_IO has been asserted. For clarity, we are assuming that a reset just took place, so the value of TIMER is 0.  

 

On Clock Cycle 2, the first DWORD is presented on AD_IO, and ADDR_VLD is asserted to the user application. Not shown in the waveforms below, ADDR is valid to the user application as well. Because ADDR_VLD is asserted, TIMER is set to whatever BL_WAIT is. BL_WAIT = number of wait states to be inserted + 3. During Clock 2, S_READY and S_TERM are set to 0, since the boolean compare (TIMER <= 4'h3) is now false. 

 

On Clock Cycle 3, BASE_HIT[x] would be asserted, signaling the transaction is targeting the Xilinx PCI device. At this point, S_READY  

and S_TERM are checked, and TRDY_IO would be asserted on the following clock if S_READY = 1. The Xilinx LogiCORE provides a medium decode for addresses, so DEVSEL_IO is asserted in time for the rising edge of Clock 3. Since S_READY and S_TERM are both de-asserted, a wait state will be inserted on Clock 4. TIMER is decremented to 4.  

 

On Clock Cycle 4, S_READY and S_TERM are checked to determine the state of TRDY_IO on Clock 5. S_READY and S_TERM are still de-asserted, so another wait state will be asserted on Clock 5. TIMER is decremented to 3 on the clock edge, so S_READY and S_TERM are asserted combinatorially during Clock 4, signaling a disconnect with data. 

 

The second (and final) wait state is inserted. S_READY and S_TERM are sampled on the rising edge of Clock 5, signaling a disconnect with data on Clock 6. TRDY_IO is asserted and STOP_IO is asserted during Clock 5 due to this. 

 

The data is transferred on the rising edge of Clock 6. According to the PCI specifications, STOP_IO is required to remain asserted, and TRDY_IO is de-asserted during Clock 6. Since FRAME_IO (and DEVSEL_IO) are still asserted, the initiator places another DWORD on the PCI bus. Since STOP is asserted on the rising edge of clock 6, FRAME_IO is de-asserted during Clock 6. 

 

Because STOP_IO is asserted and TRDY_IO is de-asserted on the rising edge of Clock 7, DEVSEL_IO is de-asserted, ending the transaction. D2 is never transferred. 

 

Insertion of Wait States in a Target Write
Insertion of Wait States in a Target Write

AR# 7300
Date Created 08/21/2007
Last Updated 05/14/2014
Status Archive
Type General Article