AR# 73052

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UltraScale/UltraScale+ DDR3/DDR4 IP - [Mig 66-119] Phy Core Regeneration and Stitching Failed

Description

Version Found: DDR4 v1.0

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

When implementing a design that includes a DDR4 IP core targeting an UltraScale/UltraScale+ device, the following errors can occur:

[Mig 66-119] Phy core regeneration & stitching failed. Please check vivado.log and debug_core_synth.log files in the directory: /sample/ddr4_pinout_test.runs/impl_1/ to debug the problem.

[Opt 31-306] MIG Core Generation Failed.

Solution

These errors are very rare and are due to an issue synthesizing certain mux conditions within the IP.

When targeting Vivado 2019.2, the errors can be resolved by applying the two patches attached to this Answer Record.  Please download the patches and review the included installation instructions.

This issue is resolved starting with Vivado 2019.2.1 where the patch is no longer required.  

Users who encounter this issue must either update to Vivado 2019.2 and install the patch or use Vivado 2019.2.1 or newer.

Revision History:

11/12/2019 - Initial Release

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AR# 73052
Date 06/10/2020
Status Active
Type Known Issues
Devices More Less
IP
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