AR# 73068

Design Advisory for UltraScale/UltraScale+ DDR4/DDR3 IP - Memory IP Timing Exceptions Might Manifest as Post Calibration Data Errors or DQS Gate Tracking Errors in Hardware

Description

Version Found: DDR4 v2.1 (Rev. 1), DDR3 v1.3 (Rev. 1) released with Vivado 2016.4

Version Resolved: See (Xilinx Answer 69035) for DDR4, See (Xilinx Answer 69036) for DDR3

Designs targeting UltraScale/UltraScale+ DDR4/DDR3 IP might encounter hardware failure modes such as post calibration data errors or post calibration DQS gate tracking issues.  These errors would occur on the first read or write access after a successful calibration. This issue does not affect PHY-ONLY or Ping Pong PHY designs.

We have determined the root cause to be a race condition upon calibration completion. The reason for the race condition is a timing exception covered by a multicycle constraint which causes it to not be flagged in timing analysis reports.

This issue is build-dependent and is based on the routing and implementation of the design, so it could potentially appear and then disappear when testing multiple build images during product development.

Additionally, the issue might only manifest on a small number of devices out of a population.

Solution

To resolve the issue, the multicycle path constraints which were intended to ease timing closure are removed, and instead pipeline stages are added to these paths.

With the multicycle constraints removed, the pipeline stages will ease timing closure while ensuring that all destinations are timed to the same fabric cycle.

These fixes are automatically included with the IP starting in Vivado and Vitis 2020.1.

For designs that are still being finalized, please download and apply one of the below patches according to the target Vivado version.

Open the design with the patched version of Vivado and update or regenerate the memory IP.



For designs already in production (Vivado 2016.4 through 2019.2.1), check if the design is susceptible to the issue by running the attached Tcl script with a fully implemented design.

This Tcl script will check if the critical paths covered by the multicycle constraints were timed to the same fabric cycle.

The purpose of this script is to check the timing for finalized designs which are in production.

  • If the timing check passes then this issue will not occur in the field.
  • If the timing check fails then the design is susceptible to the issue.

There is no way to quantify the risk or exposure level if the timing check fails, and in these cases the design should be updated with the patch.

Patches for the DDR3 and DDR4 IP are provided below in the Attachments section of the Answer Record.

The issue is resolved natively in the Vivado and Vitis 2020.1 release.

If a patch for an earlier version is required, please contact Xilinx Technical Support.

Note: The Vivado 2019.2.1 patch will generate a Warning message when launching the patched Vivado instance.

This message can be safely ignored as the IP output products are correct.

WARNING: [Common 17-306] Update version (2019.2.1_AR73068) does not match product version (2019.2.1)

Revision History

  • 03/26/2020 - Initial Release
  • 06/18/2020 - Clarified Description and Solution; Updated for Vivado 2020.1

Attachments

Associated Attachments

Linked Answer Records

Master Answer Records

AR# 73068
Date 07/31/2020
Status Active
Type Design Advisory
Devices More Less
Tools
IP