AR# 73071


UltraScale+ Integrated Block for PCI Express (Vivado 2018.3/2019.1/2019.2) - Tactical Patch for Issue Fixes



Version Found: v1.3 (Rev1)

Version Resolved and other Known Issues: (Xilinx Answer 65751)

The patch provided with this answer record fixes the following issues:

  •     Bug Fix: GT TYPE property passed to IBERT(ISI) IP.
  •     Bug Fix: x16 support is added for PCIE_X1Y1 block with GTH_QUAD231 and GTH_QUAD230 for xcku11p-ffve1517 device.
  •     Bug Fix: added Tcl option (disable_user_clock_root) to enable USER_CLOCK_ROOT.
  •     Bug Fix: fix for pcie_cq_np_req_count when External MSI-X is used.

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express


This issue is due to be fixed in a future version of the core.

The patch attached to this Answer Records contains a "readme" file which includes installation instructions.

Please install patches for corresponding versions of Vivado.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem also exists in earlier versions, but no specific testing has been performed to verify earlier versions.

Revision History:

12/15/2019 - Initial Release


Associated Attachments

AR# 73071
Date 12/16/2019
Status Active
Type General Article
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