This answer record contains the Release Notes and Known Issues for the Versal Devices Integrated Block for PCI Express IP and includes the following:
This article is part of the PCI Express Solution Centre
|(Xilinx Answer 34536)||Xilinx Solution Center for PCI Express|
Please seek technical support via the PCI Express Board. The Xilinx Forums are a great resource for technical support.
The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.
Supported devices can be found in the following locations:
The following table provides a list of tactical patches for the Versal Devices Integrated Block for PCI Express core applicable on corresponding Vivado tool versions.
|Answer Record||Core Version (After installing the Patch)||Tool Version|
Known and Resolved Issues
The following table provides known issues for the Versal Devices Integrated Block for PCI Express core, starting with v1.0, initially released in Vivado 2019.2.
Note: The "Version Found" column lists the version the problem was first discovered.
The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.
|Answer Record||Title||Version Found||Version Resolved|
|(Xilinx Answer 76357)||Timing Violations with -1LP devices in Gen4x8 configuration||2020.3||Not Resolved Yet|
|(Xilinx Answer 76230)||Unable to generate PIO example design|