AR# 73083


Versal ACAP Integrated Block for PCI Express - Release Notes and Known Issues


This answer record contains the Release Notes and Known Issues for the Versal Devices Integrated Block for PCI Express IP and includes the following:

  • General Information
  • Known and Resolved Issues
  • Revision History

This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536)Xilinx Solution Center for PCI Express


Xilinx Forums:

Please seek technical support via the PCI Express Board. The Xilinx Forums are a great resource for technical support.

The entire Xilinx Community is available to help here, and you can ask questions and collaborate with Xilinx experts to get the solutions you need.


Supported devices can be found in the following locations:

  • Open the Vivado tool -> IP Catalog, right-click on the IP and select Compatible Families.
  • For a list of new features and added device support for all versions, see the Change Log file available with the core in Vivado design tools

Tactical Patch

The following table provides a list of tactical patches for the Versal Devices Integrated Block for PCI Express core applicable on corresponding Vivado tool versions.

Answer RecordCore Version (After installing the Patch)Tool Version


Known and Resolved Issues

The following table provides known issues for the Versal Devices Integrated Block for PCI Express core, starting with v1.0, initially released in Vivado 2019.2.

Note: The "Version Found" column lists the version the problem was first discovered.

The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Answer RecordTitleVersion FoundVersion Resolved
(Xilinx Answer 76357)Timing Violations with -1LP devices in Gen4x8 configuration2020.3Not Resolved Yet


Other Information:

(Xilinx Answer 76230)Unable to generate PIO example design

Revision History:

  • 11/14/2019 - Initial Release
AR# 73083
Date 04/14/2021
Status Active
Type Release Notes
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