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  3. AR# 7309: 3.1i FPGA Editor - How do I show the attributes on multiple nets or components?
  4. AR# 73099: LogiCORE MIPI CSI-2 RX Subsystem v4.1 (rev.5) - IP can generate multiple TLAST and/or TUSER[0] pulses for the first line of each frame with RAW8 and user defined data types

AR# 73099

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LogiCORE MIPI CSI-2 RX Subsystem v4.1 (rev.5) - IP can generate multiple TLAST and/or TUSER[0] pulses for the first line of each frame with RAW8 and user defined data types

Description

The MIPI CSI-2 RX Subsystem can generate multiple TLAST and/or TUSER[0] pulses for the first line of each frame with RAW8 and user defined data types.

This behavior causes subsequent IPs to see multiple TLAST and/or TUSER[0] pulses for a line.

Solution

This issue occurs in the LogiCORE MIPI CSI-2 RX Subsystem v4.1/v4.0(Rev.1)/v4.0(Rev.2) generated from Vivado 2019.2/2019.1

This issue is fixed in Vivado 2020.1. The issue does not appear in versions prior to the 2019.1 release.

  • Vivado 2019.2 - Users can download the MIPI CSI-2 RX Subsystem patch from (Xilinx Answer 73100) to work around this issue.
  • Vivado 2019.1 - Please update Vivado version to 2020.1 to work around this issue.

It is recommended to update to the latest version of the IP.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
65242 MIPI CSI-2 Receiver Subsystem - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
73100 LogiCORE MIPI CSI-2 RX Subsystem v4.1 (rev.5) - Patch Updates for the LogiCORE MIPI CSI-2 RX Subsystem v4.1 (rev.5) N/A N/A
AR# 73099
Date 06/27/2020
Status Active
Type General Article
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