This answer record contains patch updates for the LogiCORE UHD-SDI GT v2.0 (Rev 1) in Vivado 2019.2.
This patch fixes an issue with the LogiCORE UHD-SDI GT v2.0 (Rev 1) in the Vivado 2019.2 design tools.
|Patch Rev 3||(Xilinx Answer 75339)||UHD-SDI GT v2.0 – Why is QPLL1 used when QPLL0 is selected on GTHE4 or GTYE4 at 12G-SDI?|
|(Xilinx Answer 75340)||Why is the QPLL1 not connected to UHD-SDI GT on GTY at 12G-SDI?|
|Patch Rev 2||(Xilinx Answer 73527)||Why do I have synthesis issues when selecting the CPLL in Vivado 2019.2?|
|Patch Rev 1||(Xilinx Answer 73174)||Switching between PICXO and FRACXO has no impact on the ports of the core in Vivado 2019.2|
|(Xilinx Answer 73203)||Why do I receive a Synthesis error when enabling 4 lanes in Vivado 2019.2?|
|(Xilinx Answer 73216)||Why does synthesis fails in Vivado 2019.2 when the core is configured for HD-SDI, 3G-SDI or 6G-SDI?|
See the individual Answer Records for details on which release they are fixed in.
Note: This patch will not be needed with Vivado 2020.1 and later versions.
Install the patch as per the instructions in the included README.txt file to resolve this issue.
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