AR# 73227

LogiCORE IP Video Processing Subsystem (VPSS) - Why is the example application for a ZCU104 board not running in the 2019.2 version?

Description

I have generated the Video Processing Subsystem (VPSS) example application for the ZCU104 board by following the steps in (PG231), however it does not run when launched on hardware.

I can see the output of the FSBL in the console but then the Zynq MPSoC seems to hang after the FSBL and I do not see more output in the console.

Why can I not run the VPSS example application on a ZCU104 board?

Solution

The PS DDR was configured incorrectly in the Zynq MPSoC GUI in the Video Processing Subsystem Vivado example design.

As a result, the application (which runs from DDR) cannot be launched successfully.

The FSBL is launched from On-Chip Memory (OCM) and so can be run successfully.

Users can solve this issue by changing the following configuration in the Zynq MPSoC GUI (DDR configuration page), rebuilding the Vivado design, and re-exporting the hardware to Vitis.

  • DRAM IC Bus width (per die): 16 bits
  • Bank Group Address Count (Bits): 1


 

This issue will be fixed in Vivado 2020.1.

Linked Answer Records

Master Answer Records

AR# 73227
Date 01/20/2020
Status Active
Type Known Issues
IP