The MIPI D-PHY Controller requires a 200 MHz free running clock (core_clk). This clock is used as input to generate core internal clocks.
A MIPI D-PHY TX user using internal clock sources (for example the PS output clock or MMCM) to feed a 200 MHz core_clk might see that INIT_DONE is not asserted on some of their boards.
INIT_DONE is not asserted when the IP core is generated with the line-rate configuration set to 1500 Mbps, even though IP cores with the line-rate configuration set to 1449 Mbps or 1501 Mbps are working correctly.
A MIPI D-PHY TX IP with 1500 Mbps line-rate configuration generates an internal clock module with non-optimal PLL divider/multiplier settings.
This causes the output clock to have a poor peak-to-peak jitter and phase-error performance.
If you are using a MIPI D-PHY TX IP with 1500 Mbps line-rate configuration, and are using internal clock sources (for example PS output clock or MMCM) to feed a 200 MHz core_clk then you might see INIT_DONE not asserting on some boards.
This issue can occur on MIPI D-PHY TX IP generated from Vivado 2019.2 (or previous versions) with 1500 Mbps line-rate configuration.
This issue will be fixed in Vivado 2020.1.
Vivado 2019.2 Users can download the MIPI D-PHY patch from (Xilinx Answer 73316) to fix this issue.
This patch optimizes internal MMCM divider/multiplier settings to improve internal clock peak-to-peak jitter and phase-error performance.