AR# 73373

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LogiCORE MIPI CSI-2 RX Subsystem v4.1 (rev.5) - MIPI CSI-2 RX Subsystem generated from Vivado 2019.2 does not generate all lines

Description

When using the MIPI CSI-2 RX Subsystem v4.1 (rev.5) generated in Vivado 2019.2, an issue can occur where several lines per frame are not generated by the MIPI CSI-2 RX Subsystem when the sensor/TX is operating in non-continuous clock mode.

The IP works without issues in continuous clock mode.

The MIPI CSI-2 RX core (and MIPI D-PHY RX IP) registers do not show any errors during the issue, but if an ILA is inserted on the AXI4 stream bus at MIPI CSI-2 RX core output, the total line count might be less than expected.

Solution

This issue occurs in the Vivado 2019.2 generated LogiCORE MIPI CSI-2 RX Subsystem v4.1.

This issue will be fixed in Vivado 2020.1. The issue does not appear in versions prior to the 2019.2 release.

Vivado 2019.2 - Users can download the MIPI CSI-2 RX Subsystem patch from (Xilinx Answer 73100) to work around this issue.

It is recommended to update to the latest version of the IP.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
65242 MIPI CSI-2 Receiver Subsystem - Release Notes and Known Issues for the Vivado 2015.3 tool and later versions N/A N/A

Associated Answer Records

AR# 73373
Date 03/05/2020
Status Active
Type General Article
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