AR# 73409

2019.2 - 1G/2.5G AXI Ethernet Subsystem - TLAST will be asserted for two consecutive beats when a slave deasserts TREADY before the last beat on an AXIS interface


When the slave deasserts TREADY one beat before the last one on an AXIS interface, axi_ethernet will assert TLAST for two consecutive beats as shown below:



This behavior is observed in the AXI Ethernet Buffer core where the TLAST generates for two clock cycles. The issue is due to the migration of XPM FIFO in the 2019.2 release.

Please use the attached patch to resolve this issue.


Associated Attachments

Name File Size File Type 1 MB ZIP
AR# 73409
Date 04/23/2020
Status Active
Type General Article
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