AR# 73626

2020.1 Vivado IP Release Notes - All IP Change Log Information

Description

This Answer Record contains a comprehensive list of IP change log information from Vivado 2020.1 in a single location which allows you to see all IP changes without having to install Vivado Design Suite.

Solution

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100G Multirate Ethernet MAC (MRMAC) (1.2)

* Version 1.2

* Feature Enhancement: Reference design for 10G/25GE with 1588 for driver testing and beta customer access

* Feature Enhancement: Versal GT reset helper ports added

* Feature Enhancement: PTP System Timer ports removed and Timer interface ports added (System timer instantiated internally and ports appear only if PTP Enabled).

* Feature Enhancement: Example design update and timing improvement.


100M/1G TSN Subsystem (2.0)

* Version 2.0 (Rev. 5)

* Revision change in one or more subcores


10G Ethernet MAC (15.1)

* Version 15.1 (Rev. 8)

* General: "Update for synth tool behavior: Add DONT_TOUCH attribute on some CDC registers to prevent it from being optimized in global mode, which would then result in Ciritical Warning when these registers are used as path-end points in timing constraints"



10G Ethernet PCS/PMA (10GBASE-R/KR) (6.0)

* Version 6.0 (Rev. 17)

* Bug Fix: Updating constraints for cases where txuserclk and txuserclk2 are the same.

* Revision change in one or more subcores


10G Ethernet Subsystem (3.1)

* Version 3.1 (Rev. 13)

* Revision change in one or more subcores


10G/25G Ethernet Subsystem (3.2)

* Version 3.2

* Bug Fix: Updated Versal example design for optimal usage of BUFG_GT

* Bug Fix: Axi4Lite interface updated to report axi rresp and axi_bresp as 2'b10 for invalid read address and write address.

* Feature Enhancement: Added QPLL0RESET port access provided for all the configurations

* Feature Enhancement: Added Nx25G RS-FEC multi-channel option support

* Feature Enhancement: Added new registers to AXI4Lite register map

* Other: New device support added

* Revision change in one or more subcores


1G/10G/25G Switching Ethernet Subsystem (2.5)

* Version 2.5

* Bug Fix: Updated for TIMING DRCs

* Bug Fix: Fixed CDC's

* Bug Fix: Updated the FREQ_TOLERANCE_HZ for independent_clock_bufg port

* Other: New device support added

* Revision change in one or more subcores


1G/2.5G Ethernet PCS/PMA or SGMII (16.2)

* Version 16.2

* Feature Enhancement: Updated Versal devices support

* Feature Enhancement: Updated the FREQ_TOLERANCE_HZ for independent_clock_bufg port

* Other: Updated with waivers in the XDC

* Revision change in one or more subcores


32-bit Initiator/Target for PCI (7 Series) (5.0)

* Version 5.0 (Rev. 12)

* No changes


3GPP LTE Channel Estimator (2.0)

* Version 2.0 (Rev. 17)

* No changes


3GPP LTE MIMO Decoder (3.0)

* Version 3.0 (Rev. 16)

* No changes


3GPP LTE MIMO Encoder (4.0)

* Version 4.0 (Rev. 15)

* No changes


3GPP Mixed Mode Turbo Decoder (2.0)

* Version 2.0 (Rev. 20)

* Bug Fix: Removal of debug coverage assertions to prevent memory overflow.


3GPP Turbo Encoder (5.0)

* Version 5.0 (Rev. 16)

* No changes


3GPPLTE Turbo Encoder (4.0)

* Version 4.0 (Rev. 16)

* No changes


40G/50G Ethernet Subsystem (3.1)

* Version 3.1

* Bug Fix: Axi4Lite interface updated to report axi rresp and axi_bresp as 2'b10 for invalid read address and write address.

* Feature Enhancement: GTM SYSMON changes updated in l_ethernet IP to avoid Setup Timing failures.

* Feature Enhancement: Added 50G KP2 soft RSFEC support for both GTY and GTM

* Feature Enhancement: Added new registers to AXI4Lite register map

* Feature Enhancement: Added Runtime Switching support for Versal devices

* Other: New device support added

* Revision change in one or more subcores


64-bit Initiator/Target for PCI (7 Series) (5.0)

* Version 5.0 (Rev. 11)

* No changes


7 Series FPGAs Transceivers Wizard (3.6)

* Version 3.6 (Rev. 11)

* No changes


7 Series Integrated Block for PCI Express (3.3)

* Version 3.3 (Rev. 12)

* No changes


AHB-Lite to AXI Bridge (3.0)

* Version 3.0 (Rev. 16)

* Revision change in one or more subcores


AI Engine (1.0)

* Version 1.0

* No changes


AMM Master Bridge (1.0)

* Version 1.0 (Rev. 7)

* Revision change in one or more subcores


AMM Slave Bridge (1.0)

* Version 1.0 (Rev. 11)

* Revision change in one or more subcores


AXI 1G/2.5G Ethernet Subsystem (7.2)

* Version 7.2

* Bug Fix: Fixed TLAST generation issue when the TREADY is de-asserted one clock before TLAST, and also when the TREADY de-asserted in the last beat of the transfer within the AXI Ethernet buffer

* Feature Enhancement: Added Versal devices support

* Feature Enhancement: Added support for dynamic switchable between 1000BaseX and SGMII

* Other: Refer to tri_mode_ethernet_mac v9_0 and gig_ethernet_pcs_pma v16_2 core change logs for changes in the sub cores of this core

* Revision change in one or more subcores


AXI AHBLite Bridge (3.0)

* Version 3.0 (Rev. 18)

* Revision change in one or more subcores


AXI APB Bridge (3.0)

* Version 3.0 (Rev. 16)

* No changes


AXI BRAM Controller (4.1)

* Version 4.1 (Rev. 3)

* Feature Enhancement: SystemC models added


AXI Bridge for PCI Express Gen3 Subsystem (3.0)

* Version 3.0 (Rev. 11)

* General: Renamed PR_over_PCIe to DFX_over_PCIe.        -

* Revision change in one or more subcores


AXI CAN (5.0)

* Version 5.0 (Rev. 24)

* Revision change in one or more subcores


AXI Central Direct Memory Access (4.1)

* Version 4.1 (Rev. 21)

* Revision change in one or more subcores


AXI Chip2Chip Bridge (5.0)

* Version 5.0 (Rev. 8)

* General: C2C Migration to Versal.

* Revision change in one or more subcores


AXI Clock Converter (2.1)

* Version 2.1 (Rev. 20)

* Feature Enhancement: SystemC model for AXI-Interconnect sub-blocks.

* Revision change in one or more subcores


AXI Crossbar (2.1)

* Version 2.1 (Rev. 22)

* Feature Enhancement: SystemC model for AXI-Interconnect sub-blocks.

* Revision change in one or more subcores


AXI Data FIFO (2.1)

* Version 2.1 (Rev. 20)

* Revision change in one or more subcores


AXI Data Width Converter (2.1)

* Version 2.1 (Rev. 21)

* Feature Enhancement: SystemC model for AXI-Interconnect sub-blocks.

* Revision change in one or more subcores


AXI DataMover (5.1)

* Version 5.1 (Rev. 23)

* General: Enhanced support for IP Integrator

* Revision change in one or more subcores


AXI Direct Memory Access (7.1)

* Version 7.1 (Rev. 22)

* Revision change in one or more subcores


AXI EMC (3.0)

* Version 3.0 (Rev. 21)

* Revision change in one or more subcores


AXI EPC (2.0)

* Version 2.0 (Rev. 24)

* Revision change in one or more subcores


AXI Ethernet Buffer (2.0)

* Version 2.0 (Rev. 22)

* Bug Fix: Fixed TLAST generation issue when the TREADY is de-asserted one clock before TLAST, and also when the TREADY de-asserted in the last beat of the transfer

* Feature Enhancement: Added Versal devices support


AXI Ethernet Clocking (2.0)

* Version 2.0 (Rev. 2)

* No changes


AXI EthernetLite (3.0)

* Version 3.0 (Rev. 20)

* General: Updated with waivers in the XDC

* Revision change in one or more subcores


AXI GPIO (2.0)

* Version 2.0 (Rev. 23)

* Revision change in one or more subcores


AXI HB ICAP (1.0)

* Version 1.0 (Rev. 1)

* General: Update HBICAP IP to use new xilinx.com:interface:arb_rtl:1.0 instead of xilinx.com:interface:cap_rtl:1.0 for arbiter interface


AXI HWICAP (3.0)

* Version 3.0 (Rev. 25)

* General: update hwicap IP to use new xilinx.com:interface:arb_rtl:1.0 instead of xilinx.com:interface:cap_rtl:1.0 for arbiter interface

* Revision change in one or more subcores


AXI IIC (2.0)

* Version 2.0 (Rev. 24)

* General: Added C_STATIC_TIMING_REG_WIDTH hidden parameter to increase timing width

* General: Added C_DISABLE_SETUP_VIOLATION_CHECK hidden parameter to remove violation checks

* Revision change in one or more subcores


AXI Interconnect (2.1)

* Version 2.1 (Rev. 22)

* Revision change in one or more subcores


AXI Interrupt Controller (4.1)

* Version 4.1 (Rev. 14)

* No changes


AXI Lite IPIF (3.0)

* Version 3.0 (Rev. 4)

* No changes


AXI MMU (2.1)

* Version 2.1 (Rev. 19)

* Revision change in one or more subcores


AXI Master Burst (2.0)

* Version 2.0 (Rev. 7)

* No changes


AXI Memory Init (1.0)

* Version 1.0 (Rev. 2)

* Revision change in one or more subcores


AXI Memory Mapped To PCI Express (2.9)

* Version 2.9 (Rev. 3)

* Revision change in one or more subcores


AXI Memory Mapped to Stream Mapper (1.1)

* Version 1.1 (Rev. 20)

* Revision change in one or more subcores


AXI Multi Channel Direct Memory Access (1.1)

* Version 1.1 (Rev. 2)

* Revision change in one or more subcores


AXI Performance Monitor (5.0)

* Version 5.0 (Rev. 23)

* General: Updated example design file to resolve port timing issue

* Revision change in one or more subcores


AXI Protocol Checker (2.0)

* Version 2.0 (Rev. 7)

* General: Changes in XDC file

* Revision change in one or more subcores


AXI Protocol Converter (2.1)

* Version 2.1 (Rev. 21)

* Feature Enhancement: SystemC model for AXI-Interconnect sub-blocks.

* Revision change in one or more subcores


AXI Protocol Firewall (1.1)

* Version 1.1

* New Feature: Add SI-side firewall mode

* New Feature: Add interrupt enable registers and interrupt request output

* New Feature: Add prescaler and initial delay timer for all timeouts

* New Feature: Add final address and A*USER tracking registers to help debug cause of block

* New Feature: Add DECERR/SLVERR detection as optional blocking condition

* New Feature: Conditionally mask off DECERR/SLVERR responses from SI output

* Revision change in one or more subcores


AXI Quad SPI (3.2)

* Version 3.2 (Rev. 20)

* General: Internal GUI changes.

* Revision change in one or more subcores


AXI Register Slice (2.1)

* Version 2.1 (Rev. 21)

* General: Fix behavioral sim of tied-off aresetn for auto-pipelining mode.

* Revision change in one or more subcores


AXI Sideband Utility (1.0)

* Version 1.0 (Rev. 5)

* Revision change in one or more subcores


AXI SmartConnect (1.0)

* Version 1.0 (Rev. 13)

* Feature Enhancement: Support Exclusive access by specifying CONFIG.ADVANCED_PROPERTIES {__experimental_features__ {enable_exclusive_access 1}}.

* Feature Enhancement: Support MI up to 64 when SI is 1 and all endpoint slaves are AXI4LITE

* Revision change in one or more subcores


AXI TFT Controller (2.0)

* Version 2.0 (Rev. 23)

* No changes


AXI Timebase Watchdog Timer (3.0)

* Version 3.0 (Rev. 13)

* Revision change in one or more subcores


AXI Timer (2.0)

* Version 2.0 (Rev. 23)

* General: No Functional changes

* Revision change in one or more subcores


AXI Traffic Generator (3.0)

* Version 3.0 (Rev. 7)

* General: Fixed GUI in STRMG mode

* General: Minor Bug fixes

* Revision change in one or more subcores


AXI UART16550 (2.0)

* Version 2.0 (Rev. 23)

* General: added minimum maximum range for parameter C_S_AXI_ACLK_FREQ_HZ_d in coreinfo.yml.

* Revision change in one or more subcores


AXI UltraScaleB2 Device (5.0)

* Version 5.0 (Rev. 22)

* Revision change in one or more subcores


AXI Uartlite (2.0)

* Version 2.0 (Rev. 25)

* Revision change in one or more subcores


AXI Verification IP (1.1)

* Version 1.1 (Rev. 7)

* General: update to pass log check

* Revision change in one or more subcores


AXI Video Direct Memory Access (6.3)

* Version 6.3 (Rev. 9)

* General: Implemented new XDC waiver mechanism to mask user visibility of acceptable warnings

* General: Removed redundant comments from the RTL files

* Revision change in one or more subcores


AXI Virtual FIFO Controller (2.0)

* Version 2.0 (Rev. 23)

* Revision change in one or more subcores


AXI-Stream FIFO (4.2)

* Version 4.2 (Rev. 3)

* Revision change in one or more subcores


AXI4 Debug Hub (1.0)

* Version 1.0 (Rev. 1)

* General: Adding narrow burst support

* General: Updating usage from memory to register


AXI4-Stream Accelerator Adapter (2.1)

* Version 2.1 (Rev. 16)

* No changes


AXI4-Stream Broadcaster (1.1)

* Version 1.1 (Rev. 20)

* Revision change in one or more subcores


AXI4-Stream Clock Converter (1.1)

* Version 1.1 (Rev. 22)

* Revision change in one or more subcores


AXI4-Stream Combiner (1.1)

* Version 1.1 (Rev. 19)

* Revision change in one or more subcores


AXI4-Stream Data FIFO (2.0)

* Version 2.0 (Rev. 3)

* Revision change in one or more subcores


AXI4-Stream Data Width Converter (1.1)

* Version 1.1 (Rev. 20)

* Revision change in one or more subcores


AXI4-Stream Interconnect (2.1)

* Version 2.1 (Rev. 22)

* Revision change in one or more subcores


AXI4-Stream Protocol Checker (2.0)

* Version 2.0 (Rev. 5)

* General: Register Initialization

* Revision change in one or more subcores


AXI4-Stream Register Slice (1.1)

* Version 1.1 (Rev. 21)

* General: Fix behavioral simulation of tied-off aresetn for auto-pipelining mode.

* Revision change in one or more subcores


AXI4-Stream Subset Converter (1.1)

* Version 1.1 (Rev. 21)

* Revision change in one or more subcores


AXI4-Stream Switch (1.1)

* Version 1.1 (Rev. 21)

* Revision change in one or more subcores


AXI4-Stream Verification IP (1.1)

* Version 1.1 (Rev. 7)

* Revision change in one or more subcores


AXI4-Stream to Video Out (4.0)

* Version 4.0 (Rev. 10)

* No changes


Accumulator (12.0)

* Version 12.0 (Rev. 14)

* No changes


Adder/Subtracter (12.0)

* Version 12.0 (Rev. 14)

* No changes


Advanced Encryption Standard (AES) (1.1)

* Version 1.1

* General: Initial release


Advanced I/O Wizard (1.0)

* Version 1.0 (Rev. 2)

* Revision change in one or more subcores


Audio Clock Recovery Unit (1.0)

* Version 1.0 (Rev. 1)

* No changes


Audio Formatter (1.0)

* Version 1.0 (Rev. 3)

* Revision change in one or more subcores


Aurora 64B66B (12.0)

* Version 12.0 (Rev. 2)

* General: GT Ref clock connections updated for greater than 16.375 Gbps line rate and more than 4 lanes for Versal devices

* General: GT TX and RX interface definitions modified for Versal devices

* General: Changed user clk port definition to clock_rtl for Versal devices

* General: Updated GTH based logic for CRC valid generation.

* Revision change in one or more subcores


Aurora 8B10B (11.1)

* Version 11.1 (Rev. 9)

* General: Support removed for Zynq UltraScale+ (xcu25/30) devices

* Revision change in one or more subcores


Auto-negotiation and Link Training (1.0)

* Version 1.0

* Initial release of Autonegotiation (Clause-73) and Link Training (Clause-72).


BUFG GT (1.0)

* Version 1.0

* No changes


Binary Counter (12.0)

* Version 12.0 (Rev. 14)

* No changes


Block Memory Generator (8.4)

* Version 8.4 (Rev. 4)

* No changes


CANFD (3.0)

* Version 3.0

* General: New Version of IP with known bug fixes

* General: Versal board validation

* Revision change in one or more subcores


CIC Compiler (4.0)

* Version 4.0 (Rev. 15)

* No changes


CORDIC (6.0)

* Version 6.0 (Rev. 16)

* No changes


CPRI (8.11)

* Version 8.11 (Rev. 3)

* Port Change: Added agn_line_speed input port for Agnostic mode fast auto-negotiation function.

* Port Change: Added missing output port aux_clk_out on Versal designs when the AXI management option was selected.

* Bug Fix: Fixed a bug in Versal IPI design where FREQ_Hz parameters on clock output ports were missing.

* Bug Fix: Fixed a bug in Versal where Slave FEC cores did not drive bits 14:11 of the speed_select status port.

* Bug Fix: Fixed a bug in Versal simulations where encommaalign was occasionally not set correctly.

* Bug Fix: Fixed a bug where 12.1G line rate was not available in 7 Series Zynq devices with -3 speedgrade.

* Bug Fix: Fixed a bug in some Windows 10 versions of Vivado 2019.2 where create CPRI IP caused errors with some devices.

* Feature Enhancement: New Agnostic mode features including optional port to switch line rate, sub-addresses 0 & 2 are unmodified, link negotiation disabled and 8b10b scrambling removed.

* Other: Example design now uses the actual aux_clk and freerun clock frequencies entered by the user in the GUI.

* Other: Improved example design clock domain synchronization.

* Other: Updated to use version 3.1 of the CMAC_UltraScalePLUltraScale sub IP core (Hard FEC).

* Revision change in one or more subcores


Card Management Solution Subsystem (3.0)

* Version 3.0

* General: Moved to CMC Core Firmware

* General: Fixed invalid HBM temperature issue

* General: Fixed average value calculation issue

* General: Generating QSFP ports in U200 and U250 modes

* General: Added support for U55C and U55N boards

* General: Removed demonstration testbench

* Revision change in one or more subcores


Chroma Resampler (4.0)

* Version 4.0 (Rev. 14)

* No changes


Clock Verification IP (1.0)

* Version 1.0 (Rev. 2)

* No changes


Clocking Wizard (6.0)

* Version 6.0 (Rev. 5)

* Bug Fix: Internal GUI fixes

* Other: CR Fixes


Color Correction Matrix (6.0)

* Version 6.0 (Rev. 15)

* No changes


Color Filter Array Interpolation (7.0)

* Version 7.0 (Rev. 14)

* No changes


Compact GT (1.0)

* Version 1.0 (Rev. 7)

* Revision change in one or more subcores


Complex Multiplier (6.0)

* Version 6.0 (Rev. 18)

* No changes


Concat (2.1)

* Version 2.1 (Rev. 3)

* No changes


Constant (1.1)

* Version 1.1 (Rev. 7)

* Added stub file for Custom SystemC Wrapper Support


Control, Interfaces and Processing System (2.0)

* Version 2.0

* Bug Fix: Updated the Max supported frequency for NOC from 1200 to 1080 for 2HP device.

* Bug Fix: CFU max frequency set to 300 MHz for all ES1 devices.

* Bug Fix: Added missing ports for PCIE-1 config Interfaces.

* Bug Fix: Fixed offsets for PCIE extended capabilities list.

* Bug Fix: QDMA AXI-Streaming Interface incorrect port widths.

* Bug Fix: PMU Peripheral Enable option is removed from GUI.

* Bug Fix: GEM fabric clock signals are exposed to PL.

* Bug Fix: Set NPI clock always to 300MHz.

* Bug Fix: TRACE signal Width corrected.

* Bug Fix: Disable SEM GUI for unsupported devices.

* Bug Fix: Advance options (CCI and route traffic through FPD ) for LPD/PMC masters are removed from GUI.

* Feature Enhancement: EoU changes - Change of interface, port name and GUI changes for readability.

* Feature Enhancement: Tamper setting support - Allowing users to select appropriate tamper Response and Erase BBRAM based on tamper Events.

* Feature Enhancement: Cdo change - PMC cdo split into PMC and LPD cdo.PS cdo is renamed to FPD cdo.

* Feature Enhancement: For XDMA mode 2-PF MSIX capability added.

* Feature Enhancement: Added new option s- Extended Small/Large for PCIE extended config.

* Feature Enhancement: Additional GUI options for Extended capabilities ATS/PRI, PASID and CCIX vendor ID.

* Feature Enhancement: Added CFU ports.


Convolution Encoder (9.0)

* Version 9.0 (Rev. 15)

* No changes


DDR3 SDRAM (MIG) (1.4)

* Version 1.4 (Rev. 9)

* General: Updated for 2020.1

* Revision change in one or more subcores


DDR4 SDRAM (MIG) (2.2)

* Version 2.2 (Rev. 9)

* General: Updated for 2020.1

* Revision change in one or more subcores


DDS Compiler (6.0)

* Version 6.0 (Rev. 20)

* General: Enabling hexadecimal input on GUI


DFX AXI Shutdown Manager (1.0)

* Version 1.0

* General: Initial release


DFX Bitstream Monitor (1.0)

* Version 1.0

* General: Initial release


DFX Controller (1.0)

* Version 1.0

* General: Initial Release. Previously available as the PRC core.


DFX Decoupler (1.0)

* Version 1.0

* General: Initial Release


DMA/Bridge Subsystem for PCI Express (4.1)

* Version 4.1 (Rev. 6)

* General: Added a GUI option in the "Debug" tab, to enable store_ltssm logic

* General: Shared logic not supported in the example design when Tandem is enabled.

* Revision change in one or more subcores


DP DSC AXI4-Stream to Video Out (1.0)

* Version 1.0

* No changes


DSP Macro (1.0)

* Version 1.0

* No changes


DSP48 Macro (3.0)

* Version 3.0 (Rev. 17)

* No changes


DUC/DDC Compiler (3.0)

* Version 3.0 (Rev. 15)

* No changes


Debug Bridge (3.0)

* Version 3.0 (Rev. 6)

* Revision change in one or more subcores


Debug Interface Module (1.0)

* Version 1.0

* Initial release


Discrete Fourier Transform (4.2)

* Version 4.2

* General: Support added for larger point sizes 1440, 1500, 1620, 1728, 1800, 1920, 1944, 2160, 2304, 2400, 2592, 2700, 2880, 2916, 3000, 3072, 3240


DisplayPort (9.0)

* Version 9.0 (Rev. 2)

* No changes


DisplayPort RX Subsystem (2.1)

* Version 2.1 (Rev. 7)

* Bug Fix: Fixed incorrect video mode change interrupt triggering issue

* Feature Enhancement: Support added for XCZU58DR and XCZU59DR devices

* Revision change in one or more subcores


DisplayPort TX Subsystem (2.1)

* Version 2.1 (Rev. 7)

* Bug Fix: Fixed incorrect video mode change interrupt triggering issue

* Feature Enhancement: Support added for XCZU58DR and XCZU59DR devices

* Revision change in one or more subcores


Distributed Memory Generator (8.0)

* Version 8.0 (Rev. 13)

* No changes


Divider Generator (5.1)

* Version 5.1 (Rev. 16)

* No changes


Double Data Rate Sampling (1.0)

* Version 1.0

* No changes


ECC (2.0)

* Version 2.0 (Rev. 13)

* No changes


ERNIC (2.0)

* Version 2.0

* General: Performance Improvement and Feature addition


ETRNIC (1.1)

* Version 1.1 (Rev. 3)

* No changes


FEC 5G Common Utilities (1.1)

* Version 1.1 (Rev. 1)

* No changes


FIFO Generator (13.2)

* Version 13.2 (Rev. 5)

* No changes


FIR Compiler (7.2)

* Version 7.2 (Rev. 14)

* Bug Fix: Fixed bug with coefficient reload file.

* Bug Fix: Improved error trapping behavior in the GUI.

* Bug Fix: Fixed simulator specific bug

* Feature Enhancement: Extended Symmetric Coefficient Structures for Interpolation and Decimation Filters with Super Sample Rate.

* Feature Enhancement: Improved the GUI for selecting optimizations.


Fast Fourier Transform (9.1)

* Version 9.1 (Rev. 4)

* Bug Fix: utility GUI function changed to support lte_fft. No change to functionality.


Fiber Channel 32GFC RS-FEC (1.0)

* Version 1.0 (Rev. 14)

* General: Fixed bus width warning in Versal example design.

* Revision change in one or more subcores


Fixed Interval Timer (2.0)

* Version 2.0 (Rev. 10)

* No changes


FlexO 100G RS-FEC (1.0)

* Version 1.0 (Rev. 14)

* General: Updated device support.

* Revision change in one or more subcores


Floating-point (7.1)

* Version 7.1 (Rev. 10)

* General: internal use changes. No change to functionality.


G.709 FEC Encoder/Decoder (2.4)

* Version 2.4 (Rev. 2)

* No changes


G.975.1 EFEC I.4 Encoder/Decoder (1.0)

* Version 1.0 (Rev. 18)

* No changes


G.975.1 EFEC I.7 Encoder/Decoder (2.0)

* Version 2.0 (Rev. 18)

* No changes


Gamma Correction (7.0)

* Version 7.0 (Rev. 15)

* No changes


Gamma LUT (1.0)

* Version 1.0 (Rev. 7)

* General: Revision change in one or more subcores.

* Revision change in one or more subcores


GMII to RGMII (4.1)

* Version 4.1

* General: Adding support for Versal devices

* General: Adding support for monitoring MDIO transactions with external PHY to decode operating speed


HBM IP (1.0)

* Version 1.0 (Rev. 7)

* General: Added feature to configure IP in PHY_ONLY mode.


HDCP (1.0)

* Version 1.0 (Rev. 3)

* No changes


HDCP 2.2 Cipher (1.0)

* Version 1.0 (Rev. 3)

* No changes


HDCP 2.2 Cipher for DP (1.0)

* Version 1.0

* No changes


HDCP 2.2 Montgomery Modular Multiplier (1.0)

* Version 1.0 (Rev. 2)

* No changes


HDCP 2.2 Random Number Generator (1.0)

* Version 1.0 (Rev. 1)

* No changes


HDCP 2.2 Receiver (1.0)

* Version 1.0 (Rev. 13)

* Revision change in one or more subcores


HDCP 2.2 Receiver for DisplayPort 1.4 Subsystems (1.0)

* Version 1.0 (Rev. 2)

* Revision change in one or more subcores


HDCP 2.2 Transmitter (1.0)

* Version 1.0 (Rev. 13)

* Revision change in one or more subcores


HDCP 2.2 Transmitter for DisplayPort 1.4 Subsystem (1.0)

* Version 1.0 (Rev. 2)

* Revision change in one or more subcores


HDMI 1.4/2.0 Receiver (3.0)

* Version 1.1

* No changes


HDMI 1.4/2.0 Receiver Subsystem (3.1)

* Version 3.1 (Rev. 4)

* Bug Fix: VU37P and VU47P Status changed to Production

* Feature Enhancement: Added support for 3D Audio

* Revision change in one or more subcores


HDMI 1.4/2.0 Transmitter (3.0)

* Version 2.0

* No changes


HDMI 1.4/2.0 Transmitter Subsystem (3.1)

* Version 3.1 (Rev. 4)

* Bug Fix: VU37P and VU47P Status changed to Production

* Feature Enhancement: Added support for 3D Audio

* Revision change in one or more subcores


HDMI 2.0/2.1 Receiver (1.0)

* Version 1.0

* No changes


HDMI 2.0/2.1 Transmitter (1.0)

* Version 1.0

* No changes


HDMI 2.1 Receiver Subsystem (1.0)

* Version 1.0

* General: First Release

* General: HDMI 2.1 Sink


HDMI 2.1 Transmitter Subsystem (1.0)

* Version 1.0

* General: First Release

* General: HDMI 2.1 Source


HDMI GT Controller (1.0)

* Version 1.0 (Rev. 2)

* General: Fixed Vswing register (0x84) to set the MSB bit of vswing value

* General: Enabled buffer bypass on TX

* General: Added register control to change the threshold of RX clock detection


HDMI PHY Controller (1.0)

* Version 1.0

* General: Initial version

* General: Support UltraScale+ (GTHE4 and GTYE4) Only

* General: Supports HDMI 2.1 Subsystem IPs Only


High Speed SelectIO Wizard (3.6)

* Version 3.6

* General: Removed Fractional Mode Support

* General: Fixed fifo_rden connections from fifo_empty when design has multiple strobes.


I2S Receiver (1.0)

* Version 1.0 (Rev. 4)

* General: Added support for 32-Bit LR Clock

* Revision change in one or more subcores


I2S Transmitter (1.0)

* Version 1.0 (Rev. 4)

* General: Added support for 32-bit LR Clock

* Revision change in one or more subcores


IBERT 7 Series GTH (3.0)

* Version 3.0 (Rev. 18)

* No changes


IBERT 7 Series GTP (3.0)

* Version 3.0 (Rev. 18)

* No changes


IBERT 7 Series GTX (3.0)

* Version 3.0 (Rev. 18)

* No changes


IBERT 7 Series GTZ (3.1)

* Version 3.1 (Rev. 18)

* No changes


IBERT UltraScale GTH (1.4)

* Version 1.4 (Rev. 4)

* Bug Fix: Fixed issue of System clock pin updating to default value

* Revision change in one or more subcores


IBERT UltraScale GTM (1.0)

* Version 1.0 (Rev. 7)

* Bug Fix: Fixed timing issue

* Revision change in one or more subcores


IBERT UltraScale GTY (1.3)

* Version 1.3 (Rev. 4)

* Bug Fix: Fixed issue of System clock pin updating to default value

* Bug Fix: Fixed issue with certain Refclk frequencies not available.

* Revision change in one or more subcores


IEEE 802.3 200G RS-FEC (1.0)

* Version 1.0 (Rev. 10)

* General: Updated device support.

* Revision change in one or more subcores


IEEE 802.3 25G RS-FEC (1.0)

* Version 1.0 (Rev. 16)

* General: Fixed bus width warning in Versal example design.

* Revision change in one or more subcores


IEEE 802.3 400G RS-FEC (2.0)

* Version 2.0

* Second version of the core. Added option to use hard block acceleration for the RS-FEC algorithm

* Revision change in one or more subcores


IEEE 802.3 50G RS-FEC (2.0)

* Version 2.0 (Rev. 4)

* General: Updated Versal example design for latest GT Quad revision.

* Revision change in one or more subcores


IEEE 802.3 Clause 74 FEC (1.0)

* Version 1.0 (Rev. 7)

* General: Fixed bus width warning in Versal example design.

* Revision change in one or more subcores


IEEE 802.3 Multi-channel 25G RSFEC (1.0)

* Version 1.0 (Rev. 9)

* General: Updated cmac_usplus version number

* General: User can now choose the CMAC location

* General: Updated GUI


IEEE 802.3bj 100G RS-FEC (2.0)

* Version 2.0 (Rev. 8)

* General: Removed redundant set_false_path constraint for rs_fec_ctrl configuration port in KP4 mode.

* Revision change in one or more subcores


ILA (Integrated Logic Analyzer with AXIS Interface) (1.1)

* Version 1.1

* Feature Enhancement: Added advance features

* Revision change in one or more subcores


ILA (Integrated Logic Analyzer) (6.2)

* Version 6.2 (Rev. 11)

* General: Added security attribute


IOModule (3.1)

* Version 3.1 (Rev. 6)

* General: Updated to add UART hierarchy, no functional changes


Image Enhancement (8.0)

* Version 8.0 (Rev. 15)

* No changes


In System IBERT (1.0)

* Version 1.0 (Rev. 11)

* General: Added support for Alveo devices.

* Revision change in one or more subcores


Interlaken 150G (2.4)

* Version 2.4 (Rev. 5)

* Bug Fix: Updated port enablement

* Bug Fix: Fixed the parallel AXI4-Lite read-write issue

* Other: Updated with waivers in the XDC

* Other: Added new devices

* Other: Added new UltraScale+ devices support

* Revision change in one or more subcores


Interleaver/De-interleaver (8.0)

* Version 8.0 (Rev. 15)

* No changes


JESD204 (7.2)

* Version 7.2 (Rev. 8)

* Revision change in one or more subcores


JESD204 PHY (4.0)

* Version 4.0 (Rev. 8)

* Bug Fix: NA.

* Feature Enhancement: Added support for GTHE3 and GTHE4 based devices.

* Other: NA

* Revision change in one or more subcores


JESD204C (4.2)

* Version 4.2 (Rev. 1)

* Bug Fix: None

* Feature Enhancement: Added support for GTHE3 and GTHE4 based devices.

* Feature Enhancement: Improvements to example design to allow it to be run multiple times.

* Feature Enhancement: Improved loss of lock detection circuitry.

* Other: None

* Revision change in one or more subcores


JTAG to AXI Master (1.2)

* Version 1.2 (Rev. 11)

* General: Updated device support

* Revision change in one or more subcores


LDPC Encoder/Decoder (2.0)

* Version 2.0 (Rev. 5)

* Bug Fix: Fix to example design CDC handling.

* Bug Fix: Correct example design PS application Vitus build script.


LMB BRAM Controller (4.0)

* Version 4.0 (Rev. 18)

* General: Avoid simulation warning, no functional changes


LPDDR3 SDRAM (MIG) (1.0)

* Version 1.0 (Rev. 9)

* General: Changes for 2020.1

* Revision change in one or more subcores


LTE DL Channel Encoder (4.0)

* Version 4.0 (Rev. 1)

* No changes


LTE Fast Fourier Transform (2.1)

* Version 2.1 (Rev. 2)

* Bug Fix: fix for GUI latency pane transform cycles

* Bug Fix: Remove disablement of NFFTx3 and SCALING_SCHEDULE_R3 ports when NFFT_MAX is less than or equal to 1024.

* Bug Fix: Correction to Scaling Schedule width for 1k fixed point size.

* Revision change in one or more subcores


LTE PUCCH Receiver (2.0)

* Version 2.0 (Rev. 17)

* No changes


LTE RACH Detector (3.1)

* Version 3.1 (Rev. 7)

* Revision change in one or more subcores


LTE UL Channel Decoder (4.0)

* Version 4.0 (Rev. 16)

* No changes


Local Memory Bus (LMB) 1.0 (3.0)

* Version 3.0 (Rev. 11)

* General: Do not generate unnecessary XDC constraints, no functional changes.


MIPI CSI-2 RX Controller (1.0)

* Version 1.0 (Rev. 8)

* No changes


MIPI CSI-2 RX Subsystem (5.0)

* Version 5.0

* Bug Fix: Fixed multiple beat of TUSER/TLAST issue

* Bug Fix: Fixed missing lines issue

* Feature Enhancement: Added MIPI D-PHY v2.0 Specification support with limited line-rate support (up to 3.2G)

* Other: Added VCK190 based Example Design support

* Revision change in one or more subcores


MIPI CSI-2 TX Controller (1.0)

* Version 1.0 (Rev. 4)

* No changes


MIPI CSI-2 TX Subsystem (2.1)

* Version 2.1

* Feature Enhancement: Added MIPI D-PHY v2.0 Specification support with limited line-rate support (up to 3.2G)

* Feature Enhancement: Added RAW16, RAW20 Support

* Feature Enhancement: Added Support of equal bandwidth requirement of input and output interface for Effective Pixel widths >=32

* Revision change in one or more sub cores


MIPI D-PHY (4.2)

* Version 4.2

* Feature Enhancement: Extended line-rate support up to 3.2 Gbps

* Revision change in one or more subcores


MIPI DSI TX Controller (1.0)

* Version 1.0 (Rev. 7)

* No changes


MIPI DSI TX Subsystem (2.1)

* Version 2.1

* Feature Enhancement: Added MIPI D-PHY v2.0 Specification support with limited line-rate support (up to 3.2G)

* Revision change in one or more subcores


Mailbox (2.1)

* Version 2.1 (Rev. 13)

* General: Added flip-flops to interrupt outputs to avoid clock domain crossing issues for connections to different domains


Mammoth Transcoder (1.0)

* Version 1.0

* No changes


Memory Helper Core (1.4)

* Version 1.4

* No changes


Memory Interface Generator (MIG 7 Series) (4.2)

* Version 4.2 (Rev. 1)

* No changes


MicroBlaze (11.0)

* Version 11.0 (Rev. 3)

* Feature Enhancement: Added fault tolerant support for frequency optimized pipeline

* Feature Enhancement: Improved webtalk statistics to report selected preset or template

* Other: Refined DRC metadata by de-scoping waivers to only apply to IP core. No functional changes.


MicroBlaze Debug Module (MDM) (3.2)

* Version 3.2 (Rev. 18)

* Bug Fix: Ensure that error status for AXI Memory Access From Debug only applies to the latest access.

* Other: Refined DRC metadata by de-scoping waivers to only apply to IP core. No functional changes.


MicroBlaze MCS (3.0)

* Version 3.0 (Rev. 13)

* General: Avoid subcore dependency warning for Versal ACAP

* Revision change in one or more subcores


Multiplier (12.0)

* Version 12.0 (Rev. 16)

* No changes


Multiply Adder (3.0)

* Version 3.0 (Rev. 15)

* No changes


Mutex (2.1)

* Version 2.1 (Rev. 11)

* No changes


NVMe Host Accelerator (1.0)

* Version 1.0 (Rev. 2)

* Bug Fix: Timing fixes for XPM sync reset usage

* Feature Enhancement: Made IP into a production version

* Revision change in one or more subcores


NVMe Target Controller (1.0)

* Version 1.0

* General: Initial release


NoC Clock Re-Convergent Buffer (1.0)

* Version 1.0

* No changes


NoC NIDB (1.0)

* Version 1.0

* No changes


NoC Packet Switch (1.0)

* Version 1.0

* No changes


ORAN Radio IF (1.0)

* Version 1.0

* Bug Fix: NA

* Feature Enhancement: Core moved from roe_framer_v2_1 to new oran-radio-if core

* Feature Enhancement: Added multi oDU to Spatial Stream support

* Feature Enhancement: Added dedicated PRACH BID port

* Feature Enhancement: Added dedicated PRACH UL data channel

* Other: Reduced Unsolicited ports to three.

* Other: Removed 1ms input port dependency


PCIe AXI4-Lite_Tap (1.0)

* Version 1.0

* No changes


PR AXI Shutdown Manager (1.0)

* Version 1.0 (Rev. 2)

* General: Core is discontinued and replaced by the dfx_axi_shutdown_manager.


PR Bitstream Monitor (1.0)

* Version 1.0 (Rev. 2)

* General: Core is discontinued and replaced by the dfx_bitstream_monitor.


PTP 1588 Timer and Synchronizer (1.0)

* Version 1.0

* Unknown category others: New IP


Partial Reconfiguration Controller (1.3)

* Version 1.3 (Rev. 4)

* General: Core is discontinued and replaced by the dfx_controller.


Partial Reconfiguration Decoupler (1.0)

* Version 1.0 (Rev. 9)

* General: Core is discontinued and replaced by the dfx_decoupler.


Peak Cancellation Crest Factor Reduction (6.3)

* Version 6.3 (Rev. 2)

* Feature Enhancement: Default threshold value updated to 32767 from 65000. The threshold value is considered as signed number (2's complement) internally.


Polar Encoder/Decoder (1.0)

* Version 1.0 (Rev. 5)

* Bug Fix: Fix to bare metal driver concerning BA_TABLE addresses

* Bug Fix: Fix to example design CDC handling.

* Bug Fix: Correct example design PS application Vitus build script.


Processor System Reset (5.0)

* Version 5.0 (Rev. 13)

* No changes


QDRII+ SRAM (MIG) (1.4)

* Version 1.4 (Rev. 9)

* General: Updated for 2020.1

* Revision change in one or more subcores


QDRIV SRAM (MIG) (2.0)

* Version 2.0 (Rev. 9)

* General: Updated for 2020.1

* Revision change in one or more subcores


QDRIV SRAM PHY IP (2.0)

* Version 1.2

* No changes


QSGMII (3.4)

* Version 3.4 (Rev. 8)

* Bug Fix: Driving T pins of OBUFT by a ODDR.

* Other: Changed version of helper core gig_ethernet_pcs_pma from v16_1 to v16_2

* Revision change in one or more subcores


Queue DMA Subsystem for PCI Express (4.0)

* Version 4.0
 * Feature Enhancement: Major update of the IP, please refer to (PG302) version 4.0
 * Feature Enhancement: Change include registers, Context table and ports
 * Feature Enhancement: Upgrade from previous versions of IP are not supported

* Revision change in one or more subcores


RAM-based Shift Register (12.0)

* Version 12.0 (Rev. 14)

* No changes


RAMA IP (1.1)

* Version 1.1 (Rev. 5)

* General: Updated to add TLM model for Vitis emulation

* Revision change in one or more subcores


RGB to YCrCb Color-Space Converter (7.1)

* Version 7.1 (Rev. 13)

* No changes


RLDRAM3 (MIG) (1.4)

* Version 1.4 (Rev. 9)

* General: Updated for 2020.1

* Revision change in one or more subcores


Radio over Ethernet Framer (3.0)

* Version 3.0

* Bug Fix: Oran_Mode=0   : NA

* Feature Enhancement: Oran_Mode=0 : Removed any limitation on the number of fram_ctrl ports, now they can be any number between 0 and 32 independent of fram_data_ports

* Feature Enhancement: Oran_Mode=0 : Added a parameter to let the polling function within the Framer give priority either to data (default) or to control input streams

* Feature Enhancement: Oran_Mode=0 : Added a 64-bit tuser input to allow the user to provide the transport header to be pre-pended to data and control payloads

* Feature Enhancement: Oran_Mode=0 : Added a 64-bit tuser output holding the transport header which introduced received data and control payloads

* Feature Enhancement: Oran_Mode=0 : Added a parameter to allow the buffer manager to safely store a burst of incoming packets when the number of packets to buffer is 0

* Feature Enhancement: Oran_Mode=0 : Added a parameter to let the deframer interface transfer each incoming packet without checking the Sequence Number

* Feature Enhancement: Oran_Mode=0 : Added a Bit Mask to each PC_ID port mapping so that more than a single flow can be mapped to any given antenna output

* Other: None


Reed-Solomon Decoder (9.0)

* Version 9.0 (Rev. 17)

* No changes


Reed-Solomon Encoder (9.0)

* Version 9.0 (Rev. 16)

* No changes


Reset Verification IP (1.0)

* Version 1.0 (Rev. 4)

* General: fix randomization utilized issue


SC EXIT (1.0)

* Version 1.0 (Rev. 10)

* New Feature: Support Exclusive access by propagating AxLOCK signals.


SC MMU (1.0)

* Version 1.0 (Rev. 9)

* Bug Fix: Fix A*VALID de-assertion error and bus hang when one addr segment, DECERR disabled and >1 MI.


SC SI_CONVERTER (1.0)

* Version 1.0 (Rev. 9)

* No changes


SC SPLITTER (1.0)

* Version 1.0 (Rev. 4)

* No changes


SC TRANSACTION_REGULATOR (1.0)

* Version 1.0 (Rev. 8)

* No changes


SDI RX to Video Bridge (2.0)

* Version 2.0

* No changes


SMPTE SD/HD/3G-SDI (3.0)

* Version 3.0 (Rev. 9)

* Bug Fix: Added Spartan-7 support


SMPTE UHD-SDI (1.0)

* Version 1.0 (Rev. 7)

* No changes


SMPTE UHD-SDI RX (1.0)

* Version 1.0

* No changes


SMPTE UHD-SDI RX SUBSYSTEM (2.0)

* Version 2.0 (Rev. 5)

* Bug Fix: Reverted functionality to allow user to stream with CRC errors. User can choose to receive or drop stream with CRC

* New Feature: Added 12-bit support in UHD-SDI IP

* Revision change in one or more subcores


SMPTE UHD-SDI TX (1.0)

* Version 1.0

* No changes


SMPTE UHD-SDI TX SUBSYSTEM (2.0)

* Version 2.0 (Rev. 5)

* Bug Fix: Fixed max_delay over-constraint to making it easier to meet timing

* Bug Fix: Changed vid_lock, underflow, overflow and tx_ce_err to be rising edge interrupts

* New Feature: Added Pass-Through example design with Picxo

* New Feature: Revision change in one or more subcores

* Revision change in one or more subcores


SPDIF/AES3 (2.0)

* Version 2.0 (Rev. 23)

* General: Increased the tolerance towards pulse-width calculation


SelectIO Interface Wizard (5.1)

* Version 5.1 (Rev. 15)

* General: Internal bug fixes.


Sensor Demosaic (1.0)

* Version 1.0 (Rev. 7)

* General: Revision change in one or more subcores.

* Revision change in one or more subcores


Serial RapidIO Gen2 (4.1)

* Version 4.1 (Rev. 8)

* Revision change in one or more subcores


Shell Card Management Controller Subsystem (2.2)

* Version 1.0 (Rev. 1)

* Revision change in one or more subcores


Shell Utility Build Info (1.0)

* Version 1.0

* No changes


Shell Utility MSP432 BSL CRC Generator (1.0)

* Version 1.0

* No changes


Slice (1.0)

* Version 1.0 (Rev. 2)

* No changes


SmartConnect AXI2SC Bridge (1.0)

* Version 1.0 (Rev. 7)

* No changes


SmartConnect NOC Entry Bridge (1.0)

* Version 1.0

* General: New internal IP


SmartConnect NOC Exit Bridge (1.0)

* Version 1.0

* General: New internal IP


SmartConnect NOC Router (1.0)

* Version 1.0

* General: New internal IP


SmartConnect Node (1.0)

* Version 1.0 (Rev. 11)

* Feature Enhancement: Reduce latency in low area mode


SmartConnect SC2AXI Bridge (1.0)

* Version 1.0 (Rev. 7)

* No changes


SmartConnect Switchboard (1.0)

* Version 1.0 (Rev. 6)

* No changes


Soft ECC Proxy (1.0)

* Version 1.0

* No changes


Soft Error Mitigation (4.1)

* Version 4.1 (Rev. 12)

* No changes


Soft-Decision FEC (1.1)

* Version 1.1 (Rev. 5)

* Bug Fix: Correct example design PS application Vitus build script.

* Bug Fix: RTL files/modules renamed to resolve synthesis critical warnings.


Stream Traffic Manager (1.0)

* Version 1.0

* No changes


Switch Core Top (1.0)

* Version 1.0 (Rev. 8)

* No changes


System Cache (5.0)

* Version 5.0 (Rev. 1)

* Port Change: Added Interrupt port

* Port Change: Added CCIX ports

* Port Change: Added ATS ports

* Feature Enhancement: Added support for CCIX coherency protocol

* Feature Enhancement: Added support for Atomic transactions

* Feature Enhancement: Added ATS support for address translation

* Feature Enhancement: Added support for cache maintenance transactions on slave ports

* Feature Enhancement: Added fine-grained control of AXI to coherency translations

* Feature Enhancement: Added fine-grained control of snoop behavior

* Feature Enhancement: Added ECC and parity protection for cache memory when using CCIX protocol


System ILA (1.1)

* Version 1.1 (Rev. 7)

* Bug Fix: Fixed external pin debug and width issue

* Bug Fix: Added support for CXS interface

* Revision change in one or more subcores


System Management Wizard (1.3)

* Version 1.3 (Rev. 12)

* General: Device updates. No affect to customers.


TMR Comparator (1.0)

* Version 1.0 (Rev. 3)

* No changes


TMR Inject (1.0)

* Version 1.0 (Rev. 4)

* No changes


TMR Manager (1.0)

* Version 1.0 (Rev. 5)

* No changes


TMR Soft Error Mitigation Interface (1.0)

* Version 1.0 (Rev. 13)

* Revision change in one or more subcores


TMR Voter (1.0)

* Version 1.0 (Rev. 3)

* No changes


TSN Endpoint Block (1.0)

* Version 1.0 (Rev. 6)

* Revision change in one or more subcores


TSN Tri Mode Ethernet MAC (1.0)

* Version 1.0 (Rev. 5)

* No changes


Time-Aware DMA (1.0)

* Version 1.0 (Rev. 5)

* Updated device support to match that of TSN (Parent IP)

* Revision change in one or more subcores


Timer Sync 1588 (1.2)

* Version 1.2 (Rev. 4)

* No changes


Trace S2MM (1.0)

* Version 1.0

* No changes


Tri Mode Ethernet MAC (9.0)

* Version 9.0 (Rev. 16)

* Bug Fix: Versal RGMII mode: Fixed delay values not loaded for ODELAY elements on RGMI TX_CTL and TXD

* Other: VirtexuplusHBM and Virtexuplus58g device families marked production

* Other: Added I/O delay constraints for MDIO I/F


UHD-SDI Audio (2.0)

* Version 2.0 (Rev. 2)

* General: Updated constraints to resolve timing issues


UHD-SDI GT (2.0)

* Version 2.0 (Rev. 2)

* Bug Fix: Fixed the ports enablement depending on PICXO/FRACXO selection (Xilinx Answer 73174) 

* Bug Fix: Fixed synthesis issue when line rate different than 12G-SDI (Xilinx Answer 73216)

* Bug Fix: Fixed synthesis issue for 4 lanes configuration (Xilinx Answer 73203)

* Bug Fix: Fixed synthesis issue for CPLL configuration (Xilinx Answer 73527)

* Revision change in one or more subcores


UHD-SDI Video Pattern Generator (1.0)

* Version 1.0 (Rev. 1)

* No changes


URAM Read Back (1.0)

* Version 1.0

* No changes


UltraScale 100G Ethernet Subsystem (2.6)

* Version 2.6

* Bug Fix: Removed timing constraints from the OOC XDC

* Bug Fix: Updated the watchdog timer logic

* Bug Fix: Fixed the parallel AXI4-Lite read-write issue

* Other: GT ports interface VLNV updated. Now it is same for board and part based design.

* Other: Updated with waivers in the XDC

* Revision change in one or more subcores


UltraScale FPGA Gen3 Integrated Block for PCI Express (4.4)

* Version 4.4 (Rev. 7)

* General: Added a GUI option, in "Debug" tab, to enable store_ltssm logic

* General: Fixed Gen2 Link Up issue when the IP configured to use CPLL and IBERT

* General: Fixed CPLL Calibration issue when reference clock is set to 250 MHz

* Revision change in one or more subcores


UltraScale FPGAs Transceivers Wizard (1.7)

* Version 1.7 (Rev. 8)

* Feature Enhancement: Added new transceiver configuration preset options for GTY-100GAUI_4/ GTY-50GAUI_2


UltraScale Soft Error Mitigation (3.1)

* Version 3.1 (Rev. 14)

* General: Added support for additional UltraScale+ devices


UltraScale+ 100G Ethernet Subsystem (3.1)

* Version 3.1

* Bug Fix: Removed timing constraints from the OOC XDC

* Bug Fix: Updated the watchdog timer logic

* Bug Fix: Updated the CMAC core location for GTM Dual X0Y11

* Bug Fix: Fixed the parallel AXI4-lite read-write issue

* Feature Enhancement: Added 100GAUI4 - GTY / GTM_NRZ configuration support

* Other: GT ports interface VLNV updated. Now it is same for board and part based design.

* Other: Added the xil_dut_bypass module for GTM serial ports loopback in the example design test bench

* Other: Updated with waivers in the XDC

* Other: Added new UltraScale+ devices support

* Revision change in one or more subcores


UltraScale+ Integrated Block (PCIE4) for PCI Express (1.3)

* Version 1.3 (Rev. 7)

* Feature Enhancement: Added XCVU7P_C devices support.

* Other: Added a GUI option, in "Debug" tab, to enable store_ltssm logic

* Other: Shared logic not supported in the example design when Tandem is enabled.

* Revision change in one or more subcores


UltraScale+ Integrated Block (PCIE4C) for PCI Express (1.0)

* Version 1.0 (Rev. 8)

* General: Added a GUI option, in "Debug" tab, to enable store_ltssm logic

* General: Shared logic not supported in the example design when Tandem is enabled.

* Revision change in one or more subcores


UltraScale+ PHY for PCI Express (1.0)

* Version 1.0 (Rev. 14)

* Bug Fix: TX Preset user parameter propagation from GUI to RTL wrapper

* Revision change in one or more subcores


Universal Serial XGMII Ethernet Subsystem (1.1)

* Version 1.1 (Rev. 2)

* Bug Fix: For 1G line-rate FCS errors seen when preamble bytes less than eight

* Bug Fix: Simultaneous read and write transaction on AXI4Lite I/F results in wrong read data and failure of write

* Bug Fix: Core does not assert error if an incorrect address is written to or read from

* Bug Fix: Core does not assert error when an read happens to a register whose value originates in an non-active clock domain

* Bug Fix: Broadcast, unicast, multicast stat ports are not visible if the core is not generated with flow control enabled

* Other: Signal gt_reset from register GT_RESET_REG is made clear on write

* Revision change in one or more subcores


Utility Reduced Logic (2.0)

* Version 2.0 (Rev. 4)

* No changes


Utility Vector Logic (2.0)

* Version 2.0 (Rev. 1)

* No changes


VIO (Virtual Input/Output with AXIS Interface) (1.0)

* Version 1.0 (Rev. 1)

* General: 1.Fixed Timing Issues


VIO (Virtual Input/Output) (3.0)

* Version 3.0 (Rev. 19)

* No changes


Versal ACAP DMA/Bridge Subsystem for PCI Express (2.0)

* Version 2.0

* General: Major updates on functional fixes

* Revision change in one or more subcores


Versal ACAP Integrated Block for PCI Express (1.0)

* Version 1.0 (Rev. 2)

* General: Added Versal Premium devices support

* Revision change in one or more subcores


Versal ACAP PHY for PCI Express (1.0)

* Version 1.0 (Rev. 2)

* General: Added Versal Premium devices support


Versal ACAPs Transceivers Bridge IP (1.0)

* Version 1.0

* No changes


Versal ACAPs Transceivers Reset IP (1.0)

* Version 1.0

* No changes


Versal ACAPs Transceivers Wizard (1.0)

* Version 1.0

* No changes


Versal QDRIV SRAM (1.0)

* Version 1.0 (Rev. 1)

* Added ADVANCED_TG support

* Added Debug Signal support

* Added 72Mb Memory parts

* Supported Memory clock frequency from Input clock frequency feature

* Revision change in one or more subcores


Versal Soft DDR4 Memory Controller (1.0)

* Version 1.0 (Rev. 2)

* Revision change in one or more subcores


Versal Soft RLDRAM3 Memory Controller (1.0)

* Version 1.0 (Rev. 3)

* Revision change in one or more subcores


Video AXI4S Remapper (1.0)

* Version 1.0 (Rev. 13)

* General: Revision change in one or more subcores.

* Revision change in one or more subcores


Video Color Space Conversion and Correction (1.0)

* Version 1.0 (Rev. 15)

* Revision change in one or more subcores


Video Deinterlacer (5.0)

* Version 5.0 (Rev. 15)

* Revision change in one or more subcores


Video DisplayPort 1.4 RX Subsystem (2.1)

* Version 2.1 (Rev. 2)

* Bug Fix: Single write to 00100h DPCD register will clear the CR_DONE lane status bit and SYMBOL_LOCKED status bit when bit 0 of x01FC AXI-4 lite register is set to one

* Bug Fix: Fixed incorrect video mode change interrupt triggering issue

* Bug Fix: Fixed the issue of internal FIFO overflows because of absence of gating FIFO writes until valid MSA is received

* Bug Fix: Fixed the issue in receiving 0x84 and 0x87 type secondary packets back to back

* New Feature: Added Link rate option to select 8.1 Gbps (default) or 5.4 Gbps

* Feature Enhancement: Option to include AXI IIC with DP RX Subsystem

* Feature Enhancement: Support added for XCZU58DR and XCZU59DR devices

* Revision change in one or more subcores


Video DisplayPort 1.4 TX Subsystem (2.1)

* Version 2.1 (Rev. 2)

* Bug Fix: Fixed incorrect video mode change interrupt triggering issue

* New Feature: Added Link rate option to select 8.1 Gbps (default) or 5.4 Gbps

* Feature Enhancement: TX dependency on 'Line Reset Disable' software register with address 0x0F0 has been removed irrespective of whether the resolution has reduced or normal blanking. This bit will no longer have any effect on the subsystem. Reduced blanking cases have been take care of internally

* Feature Enhancement: Support added for XCZU58DR and XCZU59DR devices

* Revision change in one or more subcores


Video Frame Buffer Read (2.1)

* Version 2.1 (Rev. 4)

* General: Added example design support for new memory Dual In Memory Module

* Revision change in one or more subcores


Video Frame Buffer Write (2.1)

* Version 2.1 (Rev. 4)

* General: Added example design support for new memory Dual In Memory Module

* Revision change in one or more subcores


Video Horizontal Chroma Resampler (1.0)

* Version 1.0 (Rev. 15)

* Revision change in one or more subcores


Video Horizontal Scaler (1.0)

* Version 1.0 (Rev. 15)

* Revision change in one or more subcores


Video In to AXI4-Stream (4.0)

* Version 4.0 (Rev. 9)

* No changes


Video Letterbox Engine (1.0)

* Version 1.0 (Rev. 15)

* Revision change in one or more subcores


Video Mixer (5.0)

* Version 5.0

* General: Added registers to program the CSC coefficients

* General: Updated example design for newer Zynq platform DIMMs. (Xilinx Answer 71961)

* Revision change in one or more subcores


Video Multi-Scaler (1.0)

* Version 1.0 (Rev. 3)

* General: Added example design support for new memory Dual In line memory module


Video On Screen Display (6.0)

* Version 6.0 (Rev. 16)

* No changes


Video PHY Controller (2.2)

* Version 2.2 (Rev. 5)

* General: Updated family support in coreinfo.yml

* Revision change in one or more subcores


Video Processing Subsystem (2.2)

* Version 2.2 (Rev. 1)

* General: Added configuration option for Deinterlacer

* Revision change in one or more subcores


Video Scene Change Detection (1.0)

* Version 1.0 (Rev. 3)

* General: Added example design support for new memory Dual In Memory Module


Video Test Pattern Generator (8.0)

* Version 8.0 (Rev. 3)

* General: Added support for AXI4 compliant YUV422 and YUV420

* Revision change in one or more subcores


Video Timing Controller (6.2)

* Version 6.2

* No changes


Video Vertical Chroma Resampler (1.0)

* Version 1.0 (Rev. 15)

* Revision change in one or more subcores


Video Vertical Scaler (1.0)

* Version 1.0 (Rev. 15)

* Revision change in one or more subcores


Video to SDI TX Bridge (2.0)

* Version 2.0

* No changes


Virtex UltraScale+ FPGAs GTM Transceivers Wizard (1.0)

* Version 1.0 (Rev. 7)

* General: Adjusted line rate range supported to match the UltraScale+ FPGAs Data Sheet

* General: Example design simulation update to use dut bypass simulation flows for PAM4 signals

* Revision change in one or more subcores


Virtex-7 FPGA Gen3 Integrated Block for PCI Express (4.3)

* Version 4.3 (Rev. 7)

* General: Added a GUI option, in "Debug" tab, to enable store_ltssm logic

* General: Shared logic not supported in the example design when Tandem is enabled.


Viterbi Decoder (9.1)

* Version 9.1 (Rev. 12)

* No changes


XADC Wizard (3.3)

* Version 3.3 (Rev. 8)

* General: New Device support. No affect.


XHMC (1.0)

* Version 1.0 (Rev. 11)

* Revision change in one or more subcores


YCrCb to RGB Color-Space Converter (7.1)

* Version 7.1 (Rev. 13)

* No changes


ZYNQ UltraScale+ SYNC IP V1_0 (1.0)

* Version 1.0 (Rev. 3)

* Revision change in one or more subcores


ZYNQ UltraScale+ VCU (1.2)

* Version 1.2 (Rev. 2)

* No changes


ZYNQ UltraScale+ VCU DDR4 Controller (1.1)

* Version 1.1 (Rev. 1)

* Revision change in one or more subcores


ZYNQ7 Processing System (5.5)

* Version 5.5 (Rev. 6)

* No changes


ZYNQ7 Processing System VIP (1.0)

* Version 1.0 (Rev. 9)

* Revision change in one or more subcores


ZYNQMPSOC Processing System VIP (1.0)

* Version 1.0 (Rev. 7)

* Revision change in one or more subcores


Zynq UltraScale+ MPSoC (3.3)

* Version 3.3 (Rev. 2)

* Bug Fix: 1. Pull-up enablement register map correction.

* Bug Fix: 2. Integration of zDDR driver icmp4 version

* Bug Fix: 3. PCW GUI changes for MAX baud rate.

* Bug Fix: 4. 16-bit wide Memory interface support.

* Bug Fix: 5. CSU enablement for Isolated Subsystem.

* Revision change in one or more subcores


Zynq UltraScale+ RF Data Converter (2.3)

* Version 2.3

* Bug Fix: Fixed clock forwarding options for gen 3 devices

* Bug Fix: Made RF analyzer configurations where MMCM cannot supply the correct fabric clock illegal

* Bug Fix: Enabled calibration freeze from API when calibration freeze real time signals are not enabled

* Bug Fix: Fixed an issue on dual ADC gen 2 devices where the PL event input to ADC tiles 226 and 227 was not being connected

* New Feature: Added DAC VOP real time signal interface

* New Feature: Added clear over range real time signal input

* Other: Updated ADC and DAC real time signal interfaces to use rfdc_rts_pins_rtl interface from IP packager

* Other: Updated ADC and DAC NCO real time signal interfaces to use rfdc_nco_pins_rtl interface from IP packager

* Other: Updated calibration freeze interface

* Other: Added examples processes to set the ADC thresholds in demonstration testbench

* Other: Updated gen 3 maximum sample rates

* Other: Updated gen 3 PLL configuration

* Other: Updated gen 3 FIFO read pointer start time

* Other: Updated gen 3 clock routing

* Other: Removed reserved calibration option for gen 3 devices

* Other: Removed reserved TDD options for gen 3 devices


audio_tpg_v1_0 (1.0)

* Version 1.0

* No changes


axi_msg (1.0)

* Version 1.0 (Rev. 6)

* No changes


axi_sg (4.1)

* Version 4.1 (Rev. 13)

* No changes


gt_subcore_ip_v1_0 (1.0)

* Version 1.0

* No changes


gtm_cntrl (1.0)

* Version 1.0 (Rev. 5)

* Feature Enhancement: Added initial support for near end PMA loopback

* Revision change in one or more subcores


interrupt_controller (3.1)

* Version 3.1 (Rev. 4)

* No changes


lib_bmg (1.0)

* Version 1.0 (Rev. 13)

* No changes


lib_cdc (1.0)

* Version 1.0 (Rev. 2)

* No changes


lib_fifo (1.0)

* Version 1.0 (Rev. 14)

* No changes


lib_pkg (1.0)

* Version 1.0 (Rev. 2)

* No changes


lib_srl_fifo (1.0)

* Version 1.0 (Rev. 2)

* No changes

AR# 73626
Date 07/26/2020
Status Active
Type Release Notes
Tools