AR# 73681

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2020.2 Clocking Wizard: Issue with simulation for periods than require > 1ps size

Description

In the 2020.2 release and previous versions, the timescale for the UNISIM is 1 ps.

If the MMCM or PLL Wizard settings result in a VCO period that is not an integer number of picoseconds, then this can cause issues in the simulation.

This issue is only observed in simulation, the period of the VCO is correct in Hardware.

For example if the user has an input frequency of 100MHz and an output of 150MHz, the Clocking Wizard might choose M =12, D=1 and O0 = 8. This will result in a VCO period of 833.333ps and an Output 0 period of 6666.6667ps.

In simulation, the Vco period will alternate between 833 and 834ps to ensure that the average period is 833.333ps.

Solution

In Vivado 2020.1 a warning was added to notify the users that their accuracy requires the Vco period to alternate to give the correct average and that this is referred to as jitter.

WARNING message seen in Simulation Console:

Warning: [Unisim MMCME5-35] Input clock has jitter @7478259000. This may cause misalignment in output clocks. Instance clk_wiz_0.MMCME5_inst

If the period of the VCO is a non-integer number in ps but the simulation does not need accuracy beyond the average period being accurate, then the warning is safe to ignore and this does not impact hardware.

If the period of the VCO is a non-integer in ps and you suspect that your simulation has an issue related to this functionally, check to verify that the issue is caused by the jitter.

To verify this, you can change the values in the Clocking Wizard to result in a VCO period that is an integer value in ps.

To change values via Tcl you can use a syntax similar to the following:

set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {100.00} CONFIG.MMCM_CLKOUT0_DIVIDE_F {8.000} ] [get_ips clk_wiz_0]

As this is a simulation only issue, another approach to verify that UNISIM 1ps resolution is the source of the simulation issue would be to change the input clock frequency in the testbench.

You can use another Clock Wizard to verify that the Input frequency/Out frequency options are valid and that the Vco frequency results in an integer value in ps.

You can maintain the same output frequency from the MMCM/PLL and validate that the rest of the simulation is correct when the clock period of the MMCM output is not alternating.

AR# 73681
Date 11/24/2020
Status Active
Type General Article
Devices More Less
IP
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