Version Found: DDR4 v2.2 (Rev. 9) DDR3 v1.4 (Rev. 9)
Version Resolved: See (Xilinx Answer 58435)
Due to a change in the DONT_TOUCH attribute in Vivado 2020.1 and later versions, DDR3 or DDR4 designs using RDIMM devices and Self-Refresh must be upgraded to Vivado 2020.1 or later.
If left locked in Vivado 2020.1 or later versions and not upgraded, then errors will occur during implementation.
This only applies to IPs generated before 2020.1 and left locked when brought in to Vivado 2020.1 or later.
If not upgraded errors similar to the following will occur during place_design:
Phase 1 Generate And Synthesize MIG Cores
ERROR: [Mig 66-99] Memory Core Error - [u_ip_name] The memory interface port c0_ddr4_ck_c[0] has an invalid IOStandard DIFF_SSTL12_DCI selected. Valid IOStandard for this port include: SSTL12_DCI.
To avoid this error, DDR3/DDR4 designs generated prior to Vivado 2020.1 must be upgraded to the latest version of the IP when brought in to Vivado 2020.1 or later.
Revision History:
06/03/2020 - Initial Release
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 58435 | MIG UltraScale - IP Release Notes and Known Issues for Vivado 2014.1 and newer tool versions | N/A | N/A |