We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 7393

4.1i CORE Generator - Virtex Variable Parallel Multiplier module latency does not match the 4K (XC4000) version of the core


Keywords: Virtex, multiplier, latency

Urgency: Standard

General Description:
The Virtex Variable Parallel Multiplier shipped in the C_IP2 release has one fewer clock latency than the 4K version, even if it is generated with both the Pipelined and Registered Output options enabled.

This happens because the inputs of the 4K multipliers in CORE Generator (the Parallel Area Optimized Multipliers) are registered by default, and there is no option for registering the inputs in the Virtex version of the module.


If you are trying to convert a 4K CORE Generator multiplier to a CORE Generator Variable Parallel Multiplier for Virtex, and you need to maintain the same latency, you must explicitly register the inputs of the Variable Parallel Multiplier in your design.
AR# 7393
Date 10/09/2003
Status Archive
Type General Article