VHDL Simulation Analyze Order: (Xilinx Solution #6250) has been updated to indicate the order in which the VHDL behavioral simulation models must be analyzed for this release.
Known Issues
1. (Xilinx Solution #7409) V2.1i COREGEN, FOUNDATION: Optional pins which are not requested still appear on the Foundation symbol for a CORE Generator Core
2. (Xilinx Solution #6853) - V2.1i COREGEN, F2.1i FOUNDATION, NGDBUILD: Unexpanded block error -- ... because one or more pins on the block ... were not found
3. (Xilinx Solution #7391) - C_IP2, V2.1i COREGEN: Virtex Variable Parallel Multiplier "Set Overrides Clear" option behaves the same way as "Clear Overrides Set"
4. ((Xilinx Solution #7393) - C_IP2, V2.1i COREGEN: Virtex Variable Parallel Multiplier module latency does not match the 4K (XC4000) version of the core