We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 7402

Virtex CLKDLL - Will the CLKDLL lock if the input frequency is below 25 MHz? If not, what will the outputs of the CLKDLL look like?


If the input to the CLKDLL is less than 25 MHz, will the CLKDLL lock? What will the outputs of the CLKDLL look like?


If the input frequency of the CLKDLL is less than 25 MHz, the CLKDLL will not lock. The CLKDLL will not lock because the input clock frequency is below the required minimum input clock frequency (CLKINLF). The CLKDLL will continuously try to achieve lock on the CLKIN signal, and the output will slew in phase, period, and duty cycle as the control logic attempts to lock on the input clock.

For more information on the CLKDLL specifications, please see the DLL timing parameters in the "Virtex 2.5 V FPGA DC and Switching Characteristics" data sheet located at:


AR# 7402
Date 12/15/2012
Status Active
Type General Article