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AR# 7411

FPGA Express - "Error:OldMap:56": Express does not have information about dedicated clock pads


Keywords: Foundation, Express, BUFG, IBUF, clock, pin, port

Urgency: Standard

General Description:
If you do not use a dedicated clock pin on the chip, you will receive the
following error in map:

Error in map 2.1i:
ERROR:OldMap:56 - The LOC constraint "P28" (a IOB location) is not valid for
symbol "Clk.PAD" (pad signal=Clk), which is being mapped to the following
site types:



When a clock buffer is inserted in a design, either by inference, instantiation, or
via the constraints editor, FPGA Express does not know if you will be using a
dedicated clock pad or not. Even if you assign the pin location constraint within
FPGA Express, it does not have detailed information about Xilinx chip pinouts.

The solution is to instantiate BOTH an IBUF and BUFG in series in your HDL code
(port -> IBUF -> BUFG -> clock pins). FPGA Express will leave this combination intact,
and the implementation tools will be able to route this using a non-dedicated IOB.


Alternatively you can check the "Create I/O pads from ports" check box in
implementation options -> translate tab.
AR# 7411
Date 08/11/2003
Status Archive
Type General Article