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AR# 7412

Virtex Configuration - Initialization timing for SelectMAP (/CS assertion, BUSY asserted)


General Description:

What is the necessary initialization timing for configuring a Virtex device in SelectMAP mode?


This Answer Record discusses the timing of CS/ and the first writing of a data word. For an in-depth discussion of Virtex configuration issues, please refer to the Xilinx Application Note (Xilinx XAPP138): "Virtex FPGA Series Configuration and Readback."

Following power-up, the Virtex device requires three clock cycles to initialize. If a data-write is attempted before this initialization, no data will be transferred. At first, it could appear that data is not being written until the second rising CCLK after CS/ is asserted, which seems to contradict the information in XAPP138. However, the waveforms for SelectMAP and serial modes assume that a BitGen-generated bitstream is being loaded. This bitstream has 32 bits of padding at its beginning, so if a bit or byte (or two) is ignored because of this initialization timing, no ill effects will result.

BUSY might be high for the first one or two clock cycles of this initialization; however, because the bitstream is padded with dummy words at the beginning, no data will be lost, and configuration will not fail because of this.

AR# 7412
Date 12/15/2012
Status Active
Type General Article