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AR# 7438

OrCad Express v9.x does not interface correctly with Xilinx A2.1 tools for XC9500 CPLDs

Description

Keywords: OrCad, Express, Capture, 9500, hplusas6, hprep6, child process, Dr. Watson

Urgency: Standard

General Description:

A customer using OrCad version 9.x in conjunction with A2.1i/F2.1i
to create a Jedec file for an XC9500 CPLD will get a message similar to
the following in the OrCad Capture Session Log:

Running Xilinx Hplusas6...
***********************************************************

Executing: 'C:\Xilinx_CPLD\bin\nt\hplusas6.exe -i <design_name> -s -a -l
Design_name.log -o Timed'
ERROR [FPG0004] Unable to run child process, error (2)
.
.
.

This will be followed by a Windows application error for the program hprep6.exe

Solution

1

There has been a change in the Xilinx CPLD fitter flow in our new Version 2.1i
software which was not reflected in the OrCAD 9.x tools. Users should contact
OrCad support to determine when this flow will be fixed.

2

Xilinx has created an inert hplusas6 executable which can be placed
in the $XILINX\bin\nt directory to work around this problem.
This executable can be found at:
http://www.xilinx.com/txpatches/pub/swhelp/orcad/or_hplus.zip

3

The CPLD fitter can be run successfully via the Xilinx Design
Manager GUI.

Procedure for implementing an XC9500 design using OrCAD 9.x:

1. Produce a netlist for the design using the OrCAD tools and open the
Xilinx Design Manager. This can be done in either of two ways:

Alternative 1 (automated flow):

a) Select TOOLS->Build from the OrCAD project menu. This should
bring up the "Xilinx M1 Build Settings" window.
(Compile the design if prompted to do so.)
b) Under the "General" tab, check the button labeled "Run the Xilinx
Design Manager instead".
c) Select OK. The M1 design manager should then open.

Alternative 2 (direct method):

a) Select TOOLS->Compile from the OrCAD project menu.
b) Invoke the Design Manager by selecting "CPLD Fitter Tools" from
the Xilinx CPLD Webpack program group under the Windows Start
menu.

2. In Design Manager, create a new project:

a) File -> New Project
b) Use Browse to set the Input Design to the EDIF netlist created by
OrCAD (in the design\compile directory). Ok.

3. Select the Part. Ok.

4. Point the Design Manager to OrCAD's CPLD macro library:

a) Select Design -> Options.
b) Select "User Defined" as the CPLD Optimization Style.
c) Click "Edit Options".
d) Go to the Translate tab.
e) Use Browse to set the Macro Search Path to the directory
capture\LIBRARY\XIL_M1\XC9500, where capture is your OrCAD
installation directory.

5. Set any of the other desired fitter options in the Basic and other tabs of
the XC9500 Implementation Options window. Ok.

6. Select a timing simulation output format if desired (Simulation Options). Ok.

7. Select Design Implement to run the fitter.

AR# 7438
Date Created 09/01/1999
Last Updated 09/27/2001
Status Archive
Type General Article