We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 7461

2.1i COREGEN, VIEWLOGIC: CORE Generator writes out Viewlogic symbol pins in reverse order for Coregen module


Keywords: view, coregen, symbol, order

Urgency: standard

General Description:
The Viewlogic symbols generated by the CORE Generator in the
2.1i release may have symbol pins attached in reverse order on the

The .vhx file lists the pins as follows:

entity mlt32x8 is
port (
a : in std_logic_vector(31 downto 0);
b : in std_logic_vector(15 downto 0);
clk : in std_logic;
p : out std_logic_vector(47 downto 0) );
end mlt32x8;

However, the input pins on the symbol appear in the
reverse order with the CLK pin on top.

This is a new problem observed on the Solaris platform with
the version of VHDL2SYM shipped with Fusion 1.4.

When Viewlogic is specified as the Vendor in the CORE
Generator "Project Options" menu, the CORE Generator creates
a temporary .VHD file containing only module ports in it and runs the Viewlogic
utility VHDL2SYM to generate a Viewlogic symbol for the CORE
Generator module. After generating the symbol, it then renames the
.VHD file to module_name.VHX.



Manually edit the pins on the generated symbol using the
Viewlogic symbol editor


- Copy the .VHX file produced by Coregen to modulename.VHD and reorder the port
list in reverse in the new .VHD file
- Run VHDL2SYM manually on this .VHD file as described in (Xilinx Solution #7462)
AR# 7461
Date 08/24/2001
Status Archive
Type General Article