General Description: FPGA Express 3.x incorrectly inverts all load (G input) signals for inferred ILD latches.
This happens when targeting all FPGA devices except for Virtex. When examining the XNF file you will see a ", INV" on the G pin of the ILD component.
Several workarounds are available:
-- Instantiate the ILD component -- Invert the Gate signal before latches that are moved into the IOB -- Disable the I/O Register Merge feature in the Express Constraints Editor -- Use registers instead of latches