The HBM2 power is limited to 10W from the PCIe 3.3V rail. The performance that can be achieved using HBM2 is limited by this power limit and varies between designs.
Under these power constraints the maximum achievable HBM2 bandwidth is 201 GB/s nominal and 316 GB/s peak.
This limitation applies to the U50 Gen3x16 XDMA, U50 Gen3x4 XDMA, and U50LV Gen3x4 XDMA Platforms.
Version Found: xilinx_u50_gen3x16_xdma_201910_1
Version Fixed: N/A
This is currently a known limitation.