AR# 75234

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Queue DMA subsystem for PCI Express (PCIe) [Vivado 2020.1] - v3.0 to v4.0 Migration Guide

Description

Vivado 2020.1 includes Queue DMA subsystem for PCI Express v4.0 which is significantly different from the previous version (v3.0) available in Vivado 2019.2.

This answer record provides a guide on migrating a design with Queue DMA subsystem for PCI Express to replace v3.0 with v4.0.


This article is part of the PCI Express Solution Centre

(Xilinx Answer 34536) Xilinx Solution Center for PCI Express

Solution

Summary of changes:

TopicQDMA v3.0QDMA v4.0
QDMA BAR size and offset128K/16KConfig Bar sizes have changed to 256K/32K
Register New registers are added and some old registers bit positions are moved
Context programing Context programming has changed, need to program new bits
New Host Profile context needs to be programmed
Ports Removed some old ports (for example, dsc_byp_out_mrkr_rsp, simple bypass ports)
Added some new ports (for example, c2h_byp_in_csh_pfch_tag)
Data ProtectionParity for streaming dataCRC and ECC for streaming data
Marker responseBypass out interface has marker responseNew interface is added ‘qsts_* which carries marker response
AXI-MM awuser and aruser bits have been modified
Slave Bridge BAR settings6 BarsNeed to update BDF table through new Slave lite CSR interface

QDMA BAR size and offset:

  • Address offset changes between QDMA v3.0 and QDMA v4.0
  • Config bar size has changed
  • Mailbox and MSI-X for PF are shifted by 128Kbytes and on VF side it is shifted by 16Kbytes

 

 

QDMA v3.0

QDMA v4.0

 

Config BAR Size

PF QDMA bar size

128Kbytes

256Kbytes

 

 

VF QDMA bar size

16Kbytes

32Kbytes

 

Mailbox

PF offset

0x2400

0x22400

offset + 128Kbytes

 

VF offset

0x1000

0x5000

offset + 16Kbytes

MSI-X

PF offset

0x10000

0x30000

0ffset + 128Kbytes

 

VF offset

0x0000

0x4000

offset + 16Kbytes

MSI-X PBA offset

PF offset

0x14000

0x34000

0ffset + 128Kbytes

 

VF offset

0x800

0x4800

offset + 16Kbytes

Registers:

  • Some of the registers are updated and some new registers are added. Please refer to (PG302).
  • In QDMA v4.0, not all registers are exposed as they are in QDMA v3.0. To save area, some debug registers are hidden in default mode.
  • To expose all registers, you will need to use a Tcl command during IP generation.
set_property CONFIG.debug_mode = DEBUG_REG_ONLY [get_ipds qdma_0]

Context Programming:

New "Host Profile" table context needs to be programmed before any context settings, refer to the "Host Profile" section in (PG302).

  • For most use cases the host profile context table will be 0's, so program 0's from address 0x804 to 0x820
  • Select 0xA in QDMA_IND_CTXT_CMD (0x844) for 'sel' field
  • Write 0x34 to address 0x844

There are some changes in the existing Context table also, so please review PG302 for each context settings.

Ports Changes:

InterfaceDescriptionQDMA v3.0QDMA v4.0
AXI-MMawuser[7:0][28:0]
 aruser[7:0][28:0]
AXI-ST H2Cdata pathm_axis_h2c_dpar (data parity)m_axis_h2c_tcrc[31:0] (CRC)
 Desc bypass out H2C Markerh2c_byp_out_mrkr_rspremoved
  NAh2c_byp_out_fmt[2:0]
AXI-ST C2Hdata paths_axis_c2h_dpar (data parity)s_axis_c2h_tcrc[31:0] (CRC)
  NAs_axis_c2h_ctrl_ecc[6:0]
 Desc bypass Simple bypassc2h_byp_in_st_sim_*removed
 Desc bypass out C2H Markerc2h_byp_out_mrkr_rspremoved
  NAc2h_byp_out_fmt[2:0]
 Desc Bypass out/in Prefetch tagNAc2h_byp_out_pfch_tag[6:0]
  NAc2h_byp_in_st_csh_pfch_tag[6:0]
TMQDMA Traffic Manager Credit outNAtm_dsc_sts_pidx[15:0]
StatusQueues statusNAqsts_out_*
    

Data Protection:

  • Streaming data in QDMA v3.0 uses parity. In QDMA v4.0, it uses CRC (IEEE 802.3 CRC-32 Polynomial)

Marker Response:

In QDMA v3.0, the marker responses signal comes out on the descriptor bypass interface.

In QDMA v4.0, Marker responses are brought out on the status ports of the queues (qsts_out_*). So, in QDMA v4.0, users do not need to enable descriptor bypass ports for the marker if they are not needed.

Slave Bridge BAR settings:

  • In QDMA v3.0, there are 6 bars given for user to program the start address, end address and address translations
  • In QDMA v4.0, there is ONLY one bar and has only the start address and end address
  • In QDMA v4.0, one bar space is split into 8 virtual bars and users can program all 8 windows as they wish
  • Programming of each window can be done by writing to the BDF table. The BDF table can be accessed through the "s_axil_csr_*" interface
    • BDF table programming (0x2420 to 0x2434)
  • Each BAR window (virtual bar) requires one BDF table entry
  • There is a Maximum of 8 windows and so 8 table entries.

Steps to set up the Slave Bridge AXI bar:

  1. Enable the Slave bridge in the core configuration GUI
  2. Set up the low address and high address in the AXI BAR tab
  3. Program one bar entry through the "s_axil_csr_*" interface

For example, to set up a 4K bar window, below is the first entry of the BDF table programming.

Offset

Program Value

Register info

0x2420

0x0

Address translation value Low

0x2424

0x0

Address translation value High

0x2428

0x0

PASID

0x242C

0x0

[11:0]: Function Number

0x2430

0xC0000001

[31:30] Read/Write Access permission

[25:0] Window Size

([25:0]*4K = actual size of the window)

0x2434

0x0

SMID

The next Entry starts at 0x2440 for second window programing.

Offset

Program Value

Register info

0x2440

0x0

Address translation value Low

0x2444

0x0

Address translation value High

0x2448

0x0

PASID

0x244C

0x0

[11:0]: Function Number

0x2450

0xC0000001

[31:30] Read/Write Access permission

[25:0] Window Size

([25:0]*4K = actual size of the window)

0x2464

0x0

SMID

Each table entry starts at every ‘h20 (0x2420, 0x2440, 0x2460, etc.).

VDM messages:

QDMA 4.0 supports up to 256Bytes in VDM messages.


Revision History:

07/12/2020 - Initial Release

AR# 75234
Date 07/15/2020
Status Active
Type General Article
IP
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